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| author | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
|---|---|---|
| committer | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
| commit | c23197a26f34f559ea9797de51e187087c039c42 (patch) | |
| tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/Target/PowerPC/PPCISelDAGToDAG.cpp | |
| parent | 1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff) | |
| download | llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.gz llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.bz2 llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.xz | |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelDAGToDAG.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index b17e54dd5a..922135571f 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -602,8 +602,8 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { case ISD::SETONE: case ISD::SETOLE: case ISD::SETOGE: - LLVM_UNREACHABLE("Should be lowered by legalize!"); - default: LLVM_UNREACHABLE("Unknown condition!"); + llvm_unreachable("Should be lowered by legalize!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOEQ: case ISD::SETEQ: return PPC::PRED_EQ; case ISD::SETUNE: @@ -634,7 +634,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { Invert = false; Other = -1; switch (CC) { - default: LLVM_UNREACHABLE("Unknown condition!"); + default: llvm_unreachable("Unknown condition!"); case ISD::SETOLT: case ISD::SETLT: return 0; // Bit #0 = SETOLT case ISD::SETOGT: @@ -653,7 +653,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { case ISD::SETOGE: case ISD::SETOLE: case ISD::SETONE: - LLVM_UNREACHABLE("Invalid branch code: should be expanded by legalize"); + llvm_unreachable("Invalid branch code: should be expanded by legalize"); // These are invalid for floating point. Assume integer. case ISD::SETULT: return 0; case ISD::SETUGT: return 1; @@ -941,7 +941,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Handle PPC32 integer and normal FP loads. assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::f64: Opcode = PPC::LFDU; break; case MVT::f32: Opcode = PPC::LFSU; break; case MVT::i32: Opcode = PPC::LWZU; break; @@ -953,7 +953,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Invalid PPC load type!"); + default: llvm_unreachable("Invalid PPC load type!"); case MVT::i64: Opcode = PPC::LDU; break; case MVT::i32: Opcode = PPC::LWZU8; break; case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; @@ -970,7 +970,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { PPCLowering.getPointerTy(), MVT::Other, Ops, 3); } else { - LLVM_UNREACHABLE("R+R preindex loads not supported yet!"); + llvm_unreachable("R+R preindex loads not supported yet!"); } } |