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author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-08-30 02:29:45 +0000 |
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committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-08-30 02:29:45 +0000 |
commit | 7248968fa529726b44d41bd25403d50c74db4bc4 (patch) | |
tree | c5982d93a8af273fdbe4e2712de1e43d2e94b4af /lib/Target/PowerPC/PPCInstr64Bit.td | |
parent | 6dc6a89d73c24f20caabda4cdcd9279e88658d0b (diff) | |
download | llvm-7248968fa529726b44d41bd25403d50c74db4bc4.tar.gz llvm-7248968fa529726b44d41bd25403d50c74db4bc4.tar.bz2 llvm-7248968fa529726b44d41bd25403d50c74db4bc4.tar.xz |
[PowerPC] Add loads, stores, and related things to fast-isel.
This is the next big chunk of fast-isel code. The primary purpose is
to implement selection of loads and stores, but there is a lot of
drag-along to support this. The common code to analyze addresses for
both loads and stores is substantial. It's also necessary to add the
materialization code for global values.
Related to load-store processing is the code to fold loads into
integer extends, since otherwise we generate lots of redundant
instructions. We also need to add some overrides to some FastEmit
routines to ensure we don't assign GPR 0 to a virtual register when
this would change the meaning of an instruction.
I added handling selection of a few binary arithmetic instructions, to
enable committing some test cases I wrote a while back.
Finally, ap couple of miscellaneous changes:
* I cleaned up some poor style from a previous patch in
PPCISelLowering.cpp, pointed out by David Blaikie.
* I enlarged the Addr.Offset field to avoid sign problems with 32-bit
offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189636 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstr64Bit.td')
-rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 92579040b6..4a8f59b1e9 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -636,6 +636,15 @@ def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), "lwax $rD, $src", LdStLHA, [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; +// For fast-isel: +let isCodeGenOnly = 1, mayLoad = 1 in { +def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), + "lwa $rD, $src", LdStLWA, []>, isPPC64, + PPC970_DGroup_Cracked; +def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), + "lwax $rD, $src", LdStLHA, []>, isPPC64, + PPC970_DGroup_Cracked; +} // end fast-isel isCodeGenOnly // Update forms. let mayLoad = 1, neverHasSideEffects = 1 in { |