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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:55:45 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:55:45 +0000 |
commit | d67768db809d6b1cfe6f7c484b3719a6103286ea (patch) | |
tree | 98319db788666275ab88d17c4b488f3de33ac9b5 /lib/Target/PowerPC/PPCInstr64Bit.td | |
parent | 2b0850b8305380244ec98e1b1c89aaf57adf3b09 (diff) | |
download | llvm-d67768db809d6b1cfe6f7c484b3719a6103286ea.tar.gz llvm-d67768db809d6b1cfe6f7c484b3719a6103286ea.tar.bz2 llvm-d67768db809d6b1cfe6f7c484b3719a6103286ea.tar.xz |
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstr64Bit.td')
-rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 646cebd85a..48ce109e59 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -32,11 +32,6 @@ def symbolLo64 : Operand<i64> { def tocentry : Operand<iPTR> { let MIOperandInfo = (ops i64imm:$imm); } -def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 - let PrintMethod = "printMemRegImm"; - let EncoderMethod = "getMemRIXEncoding"; - let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg); -} def tlsreg : Operand<i64> { let EncoderMethod = "getTLSRegEncoding"; } @@ -626,9 +621,6 @@ let canFoldAsLoad = 1, PPC970_Unit = 2 in { def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), "ld $rD, $src", LdStLD, [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; -def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), - "ld $rD, $src", LdStLD, - []>, isPPC64; // The following three definitions are selected for small code model only. // Otherwise, we need to create two instructions to form a 32-bit offset, // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). |