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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:54:54 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:54:54 +0000 |
| commit | a01c7dbaabae7cf569410bedd71361b75f65875f (patch) | |
| tree | c5d257b36bb668ba6323af7b9d58b6607676ede6 /lib/Target/PowerPC/PPCInstrFormats.td | |
| parent | 3b2552933642c19ce5e8836d82c26c562910e239 (diff) | |
| download | llvm-a01c7dbaabae7cf569410bedd71361b75f65875f.tar.gz llvm-a01c7dbaabae7cf569410bedd71361b75f65875f.tar.bz2 llvm-a01c7dbaabae7cf569410bedd71361b75f65875f.tar.xz | |
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrFormats.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 16dbee5d29..c4fd192950 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -777,16 +777,14 @@ class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, bits<5> RT; bits<5> RA; bits<5> RB; - bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12). - bits<3> CR; + bits<5> COND; let Pattern = pattern; let Inst{6-10} = RT; let Inst{11-15} = RA; let Inst{16-20} = RB; - let Inst{21-23} = CR; - let Inst{24-25} = BIBO{6-5}; + let Inst{21-25} = COND; let Inst{26-30} = xo; let Inst{31} = 0; } |