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| author | Chris Lattner <sabre@nondot.org> | 2010-11-15 08:22:03 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-11-15 08:22:03 +0000 |
| commit | b7035d04421112a4585245f67bc564170ec45b29 (patch) | |
| tree | ff86ab219c3c14c38b6b39f42e73d545d30f0ca0 /lib/Target/PowerPC/PPCInstrFormats.td | |
| parent | 17e2c188359769a1df18c42593a94ce0fc2a9a75 (diff) | |
| download | llvm-b7035d04421112a4585245f67bc564170ec45b29.tar.gz llvm-b7035d04421112a4585245f67bc564170ec45b29.tar.bz2 llvm-b7035d04421112a4585245f67bc564170ec45b29.tar.xz | |
split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrFormats.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 3949bd3d21..84a15b1ca9 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -102,6 +102,19 @@ class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; + bits<21> Addr; + + let Pattern = pattern; + + let Inst{6-10} = A; + let Inst{11-15} = Addr{20-16}; // Base Reg + let Inst{16-31} = Addr{15-0}; // Displacement +} + +class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { + bits<5> A; bits<16> C; bits<5> B; @@ -112,6 +125,7 @@ class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, let Inst{16-31} = C; } + class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>; @@ -147,8 +161,7 @@ class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { let A = 0; - let B = 0; - let C = 0; + let Addr = 0; } class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, |