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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-06-19 21:14:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-06-19 21:14:34 +0000 |
| commit | 7164288c3eb52e20454fc757440f867f04eb13a4 (patch) | |
| tree | e2599c6d8ee747086bbc76dd5a2dff8ba5339ae9 /lib/Target/PowerPC/PPCInstrInfo.h | |
| parent | d8d0279c007e70c325b4ac9d9893b31ee5f21085 (diff) | |
| download | llvm-7164288c3eb52e20454fc757440f867f04eb13a4.tar.gz llvm-7164288c3eb52e20454fc757440f867f04eb13a4.tar.bz2 llvm-7164288c3eb52e20454fc757440f867f04eb13a4.tar.xz | |
Implement PPCInstrInfo::isCoalescableExtInstr().
The PPC::EXTSW instruction preserves the low 32 bits of its input, just
like some of the x86 instructions. Use it to reduce register pressure
when the low 32 bits have multiple uses.
This requires a small change to PeepholeOptimizer since EXTSW takes a
64-bit input register.
This is related to PR5997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 7d49aa129e..374213ea43 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -92,6 +92,9 @@ public: CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const; + bool isCoalescableExtInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SubIdx) const; unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, |