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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-17 17:19:05 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-17 17:19:05 +0000 |
| commit | 1fb54cfb0a013c8ab664a6e754b34a125fe85254 (patch) | |
| tree | 176c86d7857c061dcf6e5342e47e32f51869ed60 /lib/Target/PowerPC/PPCInstrInfo.td | |
| parent | 8952d909a5d27f528abf93ee5366293d528dcf84 (diff) | |
| download | llvm-1fb54cfb0a013c8ab664a6e754b34a125fe85254.tar.gz llvm-1fb54cfb0a013c8ab664a6e754b34a125fe85254.tar.bz2 llvm-1fb54cfb0a013c8ab664a6e754b34a125fe85254.tar.xz | |
PowerPC: Mark some more patterns as isCodeGenOnly.
A couple of recently introduced conditional branch patterns
also need to be marked as isCodeGenOnly since they cannot
be handled by the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179690 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 11b18e153d..d3d96ea877 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -725,6 +725,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; + let isCodeGenOnly = 1 in def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), "b${cond:cc}ctr ${cond:reg}", BrB, []>; } @@ -788,6 +789,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), "bctrl", BrB, [(PPCbctrl)]>, Requires<[In32BitMode]>; + + let isCodeGenOnly = 1 in def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), "b${cond:cc}ctrl ${cond:reg}", BrB, []>; } |