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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:01:55 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:01:55 +0000 |
commit | 7e66f5c1b4a166d823e0452d1a1bc0f822d04201 (patch) | |
tree | 65006794a5c85537d913b10bebd3164fbd4b6aaa /lib/Target/PowerPC/PPCInstrInfo.td | |
parent | 90b1086b93708149ed7a3749e2eeccea264a037d (diff) | |
download | llvm-7e66f5c1b4a166d823e0452d1a1bc0f822d04201.tar.gz llvm-7e66f5c1b4a166d823e0452d1a1bc0f822d04201.tar.bz2 llvm-7e66f5c1b4a166d823e0452d1a1bc0f822d04201.tar.xz |
[PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.td')
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 4f006024d3..534327056b 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -926,6 +926,14 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), "b${cond:cc}ctrl ${cond:reg}", BrB, []>; } + let Uses = [LR, RM] in { + def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), + "blrl", BrB, []>; + + let isCodeGenOnly = 1 in + def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), + "b${cond:cc}lrl ${cond:reg}", BrB, []>; + } } let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in @@ -2183,6 +2191,11 @@ multiclass BranchExtendedMnemonic<string name, int bibo> { def : InstAlias<"b"#name#"ctr", (BCCTR bibo, CR0)>; + def : InstAlias<"b"#name#"lrl $cc", + (BCLRL bibo, crrc:$cc)>; + def : InstAlias<"b"#name#"lrl", + (BCLRL bibo, CR0)>; + def : InstAlias<"b"#name#"ctrl $cc", (BCCTRL bibo, crrc:$cc)>; def : InstAlias<"b"#name#"ctrl", |