This is the initial check-in for adding register scavenging to PPC. (Currently,

PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 2 deletions

diff --git a/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/lib/Target/PowerPC/PPCMachineFunctionInfo.h
index 2a8ca1ff2e..5478455ed4 100644
--- a/lib/Target/PowerPC/PPCMachineFunctionInfo.h
+++ b/lib/Target/PowerPC/PPCMachineFunctionInfo.h
@@ -35,6 +35,9 @@ private:
   /// only valid after the initial scan of the function by PEI.
   bool UsesLR;
 
+  /// SpillsCR - Indicates whether CR is spilled in the current function.
+  bool SpillsCR;
+
   /// LRStoreRequired - The bool indicates whether there is some explicit use of
   /// the LR/LR8 stack slot that is not obvious from scanning the code.  This
   /// requires that the code generator produce a store of LR to the stack on
@@ -42,7 +45,10 @@ private:
   bool LRStoreRequired;
 public:
   PPCFunctionInfo(MachineFunction &MF) 
-    : FramePointerSaveIndex(0), ReturnAddrSaveIndex(0), LRStoreRequired(false){}
+    : FramePointerSaveIndex(0),
+      ReturnAddrSaveIndex(0),
+      SpillsCR(false),
+      LRStoreRequired(false) {}
 
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
@@ -57,9 +63,11 @@ public:
   void setUsesLR(bool U) { UsesLR = U; }
   bool usesLR() const    { return UsesLR; }
 
+  void setSpillsCR()       { SpillsCR = true; }
+  bool isCRSpilled() const { return SpillsCR; }
+
   void setLRStoreRequired() { LRStoreRequired = true; }
   bool isLRStoreRequired() const { return LRStoreRequired; }
-  
 };
 
 } // end of namespace llvm