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| author | Hal Finkel <hfinkel@anl.gov> | 2012-04-01 04:44:16 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-04-01 04:44:16 +0000 |
| commit | 20b529b3f90bf17b6023ed6f8983c53c1f5be1ad (patch) | |
| tree | 02fe1981b101a6fdca3f00c9943456a727358d4d /lib/Target/PowerPC/PPCScheduleG3.td | |
| parent | 6226c49bdec886a7162e24e152af579df203e163 (diff) | |
| download | llvm-20b529b3f90bf17b6023ed6f8983c53c1f5be1ad.tar.gz llvm-20b529b3f90bf17b6023ed6f8983c53c1f5be1ad.tar.bz2 llvm-20b529b3f90bf17b6023ed6f8983c53c1f5be1ad.tar.xz | |
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG3.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG3.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index e7e5498766..bc926f7bb2 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -32,7 +32,8 @@ def G3Itineraries : ProcessorItineraries< InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>, InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>, InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, |