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| author | Jim Laskey <jlaskey@mac.com> | 2005-10-18 16:59:23 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-10-18 16:59:23 +0000 |
| commit | 21f587ca243c2265e9b8aa81481f9085cd0e7b68 (patch) | |
| tree | 2e87c7853df6c10c8f1677d446f84981b4b7d8d6 /lib/Target/PowerPC/PPCScheduleG4.td | |
| parent | 841d12d9ac489ec33d933af96d77dd4fc2a4cee2 (diff) | |
| download | llvm-21f587ca243c2265e9b8aa81481f9085cd0e7b68.tar.gz llvm-21f587ca243c2265e9b8aa81481f9085cd0e7b68.tar.bz2 llvm-21f587ca243c2265e9b8aa81481f9085cd0e7b68.tar.xz | |
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG4.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4.td | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 28fb004f62..6984ae9b0a 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -14,46 +14,32 @@ def G4Itineraries : ProcessorItineraries<G4, [ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>, InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>, InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>, InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>, - InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>, - InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>, InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>, InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>, InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>, - InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>, - InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>, InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>, InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<BrB , [InstrStage<1, [BPU]>]>, InstrItinData<BrCR , [InstrStage<1, [SRU]>]>, InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>, InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, - InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>, InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>, InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>, - InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>, InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>, InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>, - InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>, - InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>, - InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>, InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>, InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>, @@ -76,7 +62,6 @@ def G4Itineraries : ProcessorItineraries<G4, [ InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>, InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>, InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>, - InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>, InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>, |