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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:49:18 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:49:18 +0000 |
| commit | 1abaf907b6aff6e468cb838fa40e0ec6cc5ece24 (patch) | |
| tree | 8eeb038f7d25daa7ed604612ceab9f8d2b468691 /lib/Target/PowerPC/PPCScheduleG5.td | |
| parent | fad7aa792a9d642cdc9345c9cffa2b9407e2635e (diff) | |
| download | llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.gz llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.bz2 llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.xz | |
Add a SchedMachineModel for the PPC G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG5.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index 7c02ea099c..c64998d52a 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -92,3 +92,18 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>, InstrItinData<VecVSR , [InstrStage<3, [VPU]>]> ]>; + +// ===---------------------------------------------------------------------===// +// e5500 machine model for scheduling and other instruction cost heuristics. + +def G5Model : SchedMachineModel { + let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. + let MinLatency = 0; // Out-of-order dispatch. + let LoadLatency = 3; // Optimistic load latency assuming bypass. + // This is overriden by OperandCycles if the + // Itineraries are queried instead. + let MispredictPenalty = 16; + + let Itineraries = G5Itineraries; +} + |