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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
| commit | 928eb49cae286c95dceecf4442997dd561c6e3b7 (patch) | |
| tree | d65ac9dd3b6f18abc632f4d186d430e075ded25a /lib/Target/PowerPC/PPCScheduleG5.td | |
| parent | d65077a50901cbe55d8285bb1149eb8ba8210a58 (diff) | |
| download | llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.gz llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.bz2 llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.xz | |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG5.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index d28214715a..2dffc48b23 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -11,7 +11,8 @@ // //===----------------------------------------------------------------------===// -def G5Itineraries : ProcessorItineraries<[ +def G5Itineraries : ProcessorItineraries< + [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [ InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, |