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| author | Hal Finkel <hfinkel@anl.gov> | 2013-09-15 15:41:11 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-09-15 15:41:11 +0000 |
| commit | 19b59e66afa8d19c35444e0a739b467d368725d3 (patch) | |
| tree | 96b483b8ef8e1b44db2cdb42344c37248445a9bc /lib/Target/PowerPC | |
| parent | 55532adc687a87574fd79822c876b10db95cd9ee (diff) | |
| download | llvm-19b59e66afa8d19c35444e0a739b467d368725d3.tar.gz llvm-19b59e66afa8d19c35444e0a739b467d368725d3.tar.bz2 llvm-19b59e66afa8d19c35444e0a739b467d368725d3.tar.xz | |
Revert r190764: PPC: Don't restrict lvsl generation to after type legalization
This is causing test-suite failures.
Original commit message:
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190765 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index ddad9f82a2..ae046f0b7a 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7177,6 +7177,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty); if (ISD::isNON_EXTLoad(N) && VT.isVector() && TM.getSubtarget<PPCSubtarget>().hasAltivec() && + DCI.getDAGCombineLevel() == AfterLegalizeTypes && LD->getAlignment() < ABIAlignment) { // This is a type-legal unaligned Altivec load. SDValue Chain = LD->getChain(); |