Make LABEL a builtin opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 6 insertions, 14 deletions

diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index e8274f3b9e..2cd8325ce3 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -66,6 +66,9 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) {
     const char *AsmStr = MI->getOperand(0).getSymbolName();
     return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
   }
+  case PPC::LABEL: {
+    return 0;
+  }
   default:
     return 4; // PowerPC instructions are all 4 bytes
   }
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 5fb567b270..097ca91a30 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -147,7 +147,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
   // FIXME - use subtarget debug flags
   if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
-    setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+    setOperationAction(ISD::LABEL, MVT::Other, Expand);
   
   // We want to legalize GlobalAddress and ConstantPool nodes into the 
   // appropriate instructions to materialize the address.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index c519d622c5..9005963df6 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -77,13 +77,6 @@ public:
   /// This is used for addressing modes.
   virtual const TargetRegisterClass *getPointerRegClass() const;  
 
-  /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
-  /// instruction if it has one.  This is used by codegen passes that update
-  /// DWARF line number info as they modify the code.
-  virtual unsigned getDWARF_LABELOpcode() const {
-    return PPC::DWARF_LABEL;
-  }
-  
   // Return true if the instruction is a register to register move and
   // leave the source and dest operands in the passed parameters.
   //
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index c405b2b9d4..7b03f92eef 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1015,10 +1015,6 @@ def DWARF_LOC        : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
                       [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
                                   (i32 imm:$file))]>;
 
-def DWARF_LABEL      : Pseudo<(ops i32imm:$id),
-                              "\n${:private}debug_loc$id:",
-                      [(dwarf_label (i32 imm:$id))]>;
-
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Patterns
 //
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7e5d693c36..75c92615ea 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -822,7 +822,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
   if (hasInfo) {
     // Mark effective beginning of when frame pointer becomes valid.
     FrameLabelId = DebugInfo->NextLabelID();
-    BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
+    BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
   }
   
   // Adjust stack pointer: r1 += NegFrameSize.
@@ -902,7 +902,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
     
     // Mark effective beginning of when frame pointer is ready.
     unsigned ReadyLabelId = DebugInfo->NextLabelID();
-    BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
+    BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
     
     MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
                                   (IsPPC64 ? PPC::X1 : PPC::R1));