Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8

28 files changed, 593 insertions, 593 deletions

diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index b2c6038062..1900a3b6e9 100644
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -1,10 +1,10 @@
 //===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the entry points for global functions defined in the LLVM
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 6306a8ee8d..bc09f1c173 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1,10 +1,10 @@
 //===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "isel"
@@ -76,8 +76,8 @@ namespace {
     MachineFunction *F;                 // The function we are compiling into
     MachineBasicBlock *BB;              // The current MBB we are compiling
     int VarArgsFrameIndex;              // FrameIndex for start of varargs area
-    
-    /// CollapsedGepOp - This struct is for recording the intermediate results 
+
+    /// CollapsedGepOp - This struct is for recording the intermediate results
     /// used to calculate the base, index, and offset of a GEP instruction.
     struct CollapsedGepOp {
       ConstantSInt *offset; // the current offset into the struct/array
@@ -87,30 +87,30 @@ namespace {
         offset(o), index(i), size(s) {}
     };
 
-    /// FoldedGEP - This struct is for recording the necessary information to 
+    /// FoldedGEP - This struct is for recording the necessary information to
     /// emit the GEP in a load or store instruction, used by emitGEPOperation.
     struct FoldedGEP {
       unsigned base;
       unsigned index;
       ConstantSInt *offset;
       FoldedGEP() : base(0), index(0), offset(0) {}
-      FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) : 
+      FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
         base(b), index(i), offset(o) {}
     };
-    
-    /// RlwimiRec - This struct is for recording the arguments to a PowerPC 
+
+    /// RlwimiRec - This struct is for recording the arguments to a PowerPC
     /// rlwimi instruction to be output for a particular Instruction::Or when
     /// we recognize the pattern for rlwimi, starting with a shift or and.
-    struct RlwimiRec { 
+    struct RlwimiRec {
       Value *Target, *Insert;
       unsigned Shift, MB, ME;
       RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
       RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
         Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
     };
-    
+
     // External functions we may use in compiling the Module
-    Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn, 
+    Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
       *__umoddi3Fn,  *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
       *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
 
@@ -126,7 +126,7 @@ namespace {
 
     // GEPMap - Mapping between basic blocks and GEP definitions
     std::map<GetElementPtrInst*, FoldedGEP> GEPMap;
-    
+
     // RlwimiMap  - Mapping between BinaryOperand (Or) instructions and info
     // needed to properly emit a rlwimi instruction in its place.
     std::map<Instruction *, RlwimiRec> InsertMap;
@@ -140,7 +140,7 @@ namespace {
     // flag to set whether or not we need to emit it for this function.
     unsigned GlobalBaseReg;
     bool GlobalBaseInitialized;
-    
+
     PPC32ISel(TargetMachine &tm):TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
       F(0), BB(0) {}
 
@@ -296,8 +296,8 @@ namespace {
                         MachineBasicBlock *MBB,
                         MachineBasicBlock::iterator MBBI);
     void visitSelectInst(SelectInst &SI);
-    
-    
+
+
     // Memory Instructions
     void visitLoadInst(LoadInst &I);
     void visitStoreInst(StoreInst &I);
@@ -305,7 +305,7 @@ namespace {
     void visitAllocaInst(AllocaInst &I);
     void visitMallocInst(MallocInst &I);
     void visitFreeInst(FreeInst &I);
-    
+
     // Other operators
     void visitShiftInst(ShiftInst &I);
     void visitPHINode(PHINode &I) {}      // PHI nodes handled by second pass
@@ -342,10 +342,10 @@ namespace {
     /// emitBitfieldInsert - return true if we were able to fold the sequence of
     /// instructions into a bitfield insert (rlwimi).
     bool emitBitfieldInsert(User *OpUser, unsigned DestReg);
-                                  
+
     /// emitBitfieldExtract - return true if we were able to fold the sequence
     /// of instructions into a bitfield extract (rlwinm).
-    bool emitBitfieldExtract(MachineBasicBlock *MBB, 
+    bool emitBitfieldExtract(MachineBasicBlock *MBB,
                              MachineBasicBlock::iterator IP,
                              User *OpUser, unsigned DestReg);
 
@@ -353,13 +353,13 @@ namespace {
     /// arithmetic and logical operations with constants on a register rather
     /// than a Value.
     ///
-    void emitBinaryConstOperation(MachineBasicBlock *MBB, 
+    void emitBinaryConstOperation(MachineBasicBlock *MBB,
                                   MachineBasicBlock::iterator IP,
-                                  unsigned Op0Reg, ConstantInt *Op1, 
+                                  unsigned Op0Reg, ConstantInt *Op1,
                                   unsigned Opcode, unsigned DestReg);
 
-    /// emitSimpleBinaryOperation - Implement simple binary operators for 
-    /// integral types.  OperatorClass is one of: 0 for Add, 1 for Sub, 
+    /// emitSimpleBinaryOperation - Implement simple binary operators for
+    /// integral types.  OperatorClass is one of: 0 for Add, 1 for Sub,
     /// 2 for And, 3 for Or, 4 for Xor.
     ///
     void emitSimpleBinaryOperation(MachineBasicBlock *BB,
@@ -380,10 +380,10 @@ namespace {
     void doMultiply(MachineBasicBlock *MBB,
                     MachineBasicBlock::iterator IP,
                     unsigned DestReg, Value *Op0, Value *Op1);
-  
+
     /// doMultiplyConst - This method will multiply the value in Op0Reg by the
     /// value of the ContantInt *CI
-    void doMultiplyConst(MachineBasicBlock *MBB, 
+    void doMultiplyConst(MachineBasicBlock *MBB,
                          MachineBasicBlock::iterator IP,
                          unsigned DestReg, Value *Op0, ConstantInt *CI);
 
@@ -406,9 +406,9 @@ namespace {
     void emitShiftOperation(MachineBasicBlock *MBB,
                             MachineBasicBlock::iterator IP,
                             Value *Op, Value *ShiftAmount, bool isLeftShift,
-                            const Type *ResultTy, ShiftInst *SI, 
+                            const Type *ResultTy, ShiftInst *SI,
                             unsigned DestReg);
-      
+
     /// emitSelectOperation - Common code shared between visitSelectInst and the
     /// constant expression support.
     ///
@@ -468,7 +468,7 @@ namespace {
     }
     unsigned getReg(Value *V, MachineBasicBlock *MBB,
                     MachineBasicBlock::iterator IPt);
-    
+
     /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
     /// is okay to use as an immediate argument to a certain binary operation
     bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
@@ -542,7 +542,7 @@ bool PPC32ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
 
   // Treat subfic like addi for the purposes of constant validation
   if (Opcode == 5) Opcode = 0;
-      
+
   // addi, subfic, compare, and non-indexed load take SIMM
   bool cond1 = (Opcode < 2)
     && ((int32_t)CI->getRawValue() <= 32767)
@@ -578,7 +578,7 @@ unsigned PPC32ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
   unsigned TySize = TM.getTargetData().getTypeSize(Ty);
   TySize *= CUI->getValue();   // Get total allocated size...
   unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
-      
+
   // Create a new stack object using the frame manager...
   int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
   AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
@@ -641,7 +641,7 @@ void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
         abort();
       }
     }
-    
+
     assert(Class <= cInt && "Type not handled yet!");
 
     // Handle bool
@@ -649,7 +649,7 @@ void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
       BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
       return;
     }
-    
+
     // Handle int
     if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
       unsigned uval = CUI->getValue();
@@ -695,7 +695,7 @@ void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
   } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
     // GV is located at base + distance
     unsigned TmpReg = makeAnotherReg(GV->getType());
-    
+
     // Move value at base + distance into return reg
     BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
       .addReg(getGlobalBaseReg()).addGlobalAddress(GV);
@@ -718,7 +718,7 @@ void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
   unsigned GPR_remaining = 8;
   unsigned FPR_remaining = 13;
   unsigned GPR_idx = 0, FPR_idx = 0;
-  static const unsigned GPR[] = { 
+  static const unsigned GPR[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
@@ -726,9 +726,9 @@ void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
     PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
     PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
   };
-    
+
   MachineFrameInfo *MFI = F->getFrameInfo();
- 
+
   for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
        I != E; ++I) {
     bool ArgLive = !I->use_empty();
@@ -823,7 +823,7 @@ void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
       }
 
       // doubles require 4 additional bytes and use 2 GPRs of param space
-      ArgOffset += 4;   
+      ArgOffset += 4;
       if (GPR_remaining > 0) {
         GPR_remaining--;
         GPR_idx++;
@@ -1004,7 +1004,7 @@ static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
   if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V)) {
     bool AllUsesAreMem = true;
-    for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end(); 
+    for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
          I != E; ++I) {
       Instruction *User = cast<Instruction>(*I);
 
@@ -1111,7 +1111,7 @@ void PPC32ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
   const Type *CompTy = Op0->getType();
   unsigned Class = getClassB(CompTy);
   unsigned Op0r = ExtendOrClear(MBB, IP, Op0);
-  
+
   // Use crand for lt, gt and crandc for le, ge
   unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
   // ? cr1[lt] : cr1[gt]
@@ -1126,7 +1126,7 @@ void PPC32ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
     if (Class == cByte || Class == cShort || Class == cInt) {
       unsigned Op1v = CI->getRawValue() & 0xFFFF;
       unsigned OpClass = (CompTy->isSigned()) ? 0 : 2;
-      
+
       // Treat compare like ADDI for the purposes of immediate suitability
       if (canUseAsImmediateForOpcode(CI, OpClass, false)) {
         BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
@@ -1227,7 +1227,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
   const Type *Ty = Op0->getType();
   unsigned Class = getClassB(Ty);
   unsigned Opcode = I.getOpcode();
-  unsigned OpNum = getSetCCNumber(Opcode);      
+  unsigned OpNum = getSetCCNumber(Opcode);
   unsigned DestReg = getReg(I);
 
   // If the comparison type is byte, short, or int, then we can emit a
@@ -1238,7 +1238,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
 
     if (CI && CI->getRawValue() == 0) {
       unsigned Op0Reg = ExtendOrClear(BB, MI, Op0);
-    
+
       // comparisons against constant zero and negative one often have shorter
       // and/or faster sequences than the set-and-branch general case, handled
       // below.
@@ -1249,13 +1249,13 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
         BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(TempReg).addImm(27)
           .addImm(5).addImm(31);
         break;
-        } 
+        }
       case 1: { // ne0
         unsigned TempReg = makeAnotherReg(Type::IntTy);
         BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
         BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
         break;
-        } 
+        }
       case 2: { // lt0, always false if unsigned
         if (Ty->isSigned())
           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(1)
@@ -1265,7 +1265,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
         break;
         }
       case 3: { // ge0, always true if unsigned
-        if (Ty->isSigned()) { 
+        if (Ty->isSigned()) {
           unsigned TempReg = makeAnotherReg(Type::IntTy);
           BuildMI(*BB, MI, PPC::RLWINM, 4, TempReg).addReg(Op0Reg).addImm(1)
             .addImm(31).addImm(31);
@@ -1278,7 +1278,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
       case 4: { // gt0, equivalent to ne0 if unsigned
         unsigned Temp1 = makeAnotherReg(Type::IntTy);
         unsigned Temp2 = makeAnotherReg(Type::IntTy);
-        if (Ty->isSigned()) { 
+        if (Ty->isSigned()) {
           BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
           BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
@@ -1292,7 +1292,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
       case 5: { // le0, equivalent to eq0 if unsigned
         unsigned Temp1 = makeAnotherReg(Type::IntTy);
         unsigned Temp2 = makeAnotherReg(Type::IntTy);
-        if (Ty->isSigned()) { 
+        if (Ty->isSigned()) {
           BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
           BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
@@ -1316,7 +1316,7 @@ void PPC32ISel::visitSetCondInst(SetCondInst &I) {
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   ilist<MachineBasicBlock>::iterator It = BB;
   ++It;
-  
+
   //  thisMBB:
   //  ...
   //   cmpTY cr0, r1, r2
@@ -1357,12 +1357,12 @@ void PPC32ISel::visitSelectInst(SelectInst &SI) {
   emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
                       SI.getFalseValue(), DestReg);
 }
- 
+
 /// emitSelect - Common code shared between visitSelectInst and the constant
 /// expression support.
 void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator IP,
-                                    Value *Cond, Value *TrueVal, 
+                                    Value *Cond, Value *TrueVal,
                                     Value *FalseVal, unsigned DestReg) {
   unsigned SelectClass = getClassB(TrueVal->getType());
   unsigned Opcode;
@@ -1491,7 +1491,7 @@ void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
   BB = sinkMBB;
   BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
     .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
-    
+
   // For a register pair representing a long value, define the top part.
   if (getClassB(TrueVal->getType()) == cLong)
     BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(FalseValue+1)
@@ -1602,15 +1602,15 @@ void PPC32ISel::visitBranchInst(BranchInst &BI) {
   BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
   if (BI.isConditional())
     BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
-  
+
   BasicBlock *NextBB = getBlockAfter(BI.getParent());  // BB after current one
 
   if (!BI.isConditional()) {  // Unconditional branch?
-    if (BI.getSuccessor(0) != NextBB) 
+    if (BI.getSuccessor(0) != NextBB)
       BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     return;
   }
-  
+
   // See if we can fold the setcc into the branch itself...
   SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
   if (SCI == 0) {
@@ -1638,7 +1638,7 @@ void PPC32ISel::visitBranchInst(BranchInst &BI) {
   unsigned Opcode = getPPCOpcodeForSetCCOpcode(SCI->getOpcode());
   MachineBasicBlock::iterator MII = BB->end();
   EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
-  
+
   if (BI.getSuccessor(0) != NextBB) {
     BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
       .addMBB(MBBMap[BI.getSuccessor(0)])
@@ -1684,7 +1684,7 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
       default: assert(0 && "Unknown class!");
       }
 
-    // Just to be safe, we'll always reserve the full 24 bytes of linkage area 
+    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
     // plus 32 bytes of argument space in case any called code gets funky on us.
     if (NumBytes < 56) NumBytes = 56;
 
@@ -1696,16 +1696,16 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
     // Offset to the paramater area on the stack is 24.
     int GPR_remaining = 8, FPR_remaining = 13;
     unsigned GPR_idx = 0, FPR_idx = 0;
-    static const unsigned GPR[] = { 
+    static const unsigned GPR[] = {
       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
     static const unsigned FPR[] = {
-      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, 
-      PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, 
+      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
+      PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
       PPC::F13
     };
-    
+
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
       unsigned ArgReg;
       switch (getClassB(Args[i].Ty)) {
@@ -1714,7 +1714,7 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
         // Promote arg to 32 bits wide into a temporary register...
         ArgReg = makeAnotherReg(Type::UIntTy);
         promote32(ArgReg, Args[i]);
-          
+
         // Reg or stack?
         if (GPR_remaining > 0) {
           BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
@@ -1772,7 +1772,7 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
           CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
           FPR_remaining--;
           FPR_idx++;
-          
+
           // If this is a vararg function, and there are GPRs left, also
           // pass the float in an int.  Otherwise, put it on the stack.
           if (isVarArg) {
@@ -1801,7 +1801,7 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
           if (isVarArg) {
             BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
             .addReg(PPC::R1);
-            
+
             // Doubles can be split across reg + stack for varargs
             if (GPR_remaining > 0) {
               BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
@@ -1823,7 +1823,7 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
         GPR_remaining--;
         GPR_idx++;
         break;
-        
+
       default: assert(0 && "Unknown class!");
       }
       ArgOffset += 4;
@@ -1833,10 +1833,10 @@ void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
   } else {
     BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
   }
-  
+
   BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
   BB->push_back(CallMI);
-  
+
   // These functions are automatically eliminated by the prolog/epilog pass
   BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
 
@@ -1893,7 +1893,7 @@ void PPC32ISel::visitCallInst(CallInst &CI) {
   unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
   bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
   doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
-}         
+}
 
 
 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
@@ -1980,7 +1980,7 @@ void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
   case Intrinsic::vastart:
     // Get the address of the first vararg value...
     TmpReg1 = getReg(CI);
-    addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex, 
+    addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
                       0, false);
     return;
 
@@ -1996,7 +1996,7 @@ void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
       MachineFrameInfo *MFI = F->getFrameInfo();
       unsigned NumBytes = MFI->getStackSize();
-      
+
       BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
         .addReg(PPC::R1);
     } else {
@@ -2014,7 +2014,7 @@ void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
       BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
     }
     return;
-    
+
 #if 0
     // This may be useful for supporting isunordered
   case Intrinsic::isnan:
@@ -2028,7 +2028,7 @@ void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
     return;
 #endif
-    
+
   default: assert(0 && "Error: unknown intrinsics should have been lowered!");
   }
 }
@@ -2051,7 +2051,7 @@ void PPC32ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
       .addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
     return;
   }
-    
+
   unsigned Class = getClassB(B.getType());
   Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
   emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
@@ -2102,7 +2102,7 @@ static unsigned ExactLog2(unsigned Val) {
 // not, since all 1's are not contiguous.
 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
   bool isRun = true;
-  MB = 0; 
+  MB = 0;
   ME = 0;
 
   // look for first set bit
@@ -2114,7 +2114,7 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
       break;
     }
   }
-  
+
   // look for last set bit
   for (; i < 32; i++) {
     if ((Val & (1 << (31 - i))) == 0)
@@ -2127,7 +2127,7 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) != 0)
       break;
   }
-  
+
   // if we exhausted all the bits, we found a match at this point for 0*1*0*
   if (i == 32)
     return true;
@@ -2143,7 +2143,7 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) == 0)
       break;
   }
-  
+
   // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
   // the value is not a run of ones.
   if (i == 32)
@@ -2156,12 +2156,12 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
 /// second operand is a constant int.  Optionally, set OrI to the Or instruction
 /// that is the sole user of OpUser, and Op1User to the other operand of the Or
 /// instruction.
-static bool isInsertAndHalf(User *OpUser, Instruction **Op1User, 
+static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
                             Instruction **OrI, unsigned &Mask) {
   // If this instruction doesn't have one use, then return false.
   if (!OpUser->hasOneUse())
     return false;
-  
+
   Mask = 0xFFFFFFFF;
   if (BinaryOperator *BO = dyn_cast<BinaryOperator>(OpUser))
     if (BO->getOpcode() == Instruction::And) {
@@ -2190,13 +2190,13 @@ static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
 /// instruction that is either used directly by the or instruction, or is used
 /// by an and instruction whose second operand is a constant int, and which is
 /// used by the or instruction.
-static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User, 
-                              Instruction **OrI, Instruction **OptAndI, 
+static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
+                              Instruction **OrI, Instruction **OptAndI,
                               unsigned &Shift, unsigned &Mask) {
   // If this instruction doesn't have one use, then return false.
   if (!OpUser->hasOneUse())
     return false;
-  
+
   Mask = 0xFFFFFFFF;
   if (ShiftInst *SI = dyn_cast<ShiftInst>(OpUser)) {
     if (ConstantInt *CI = dyn_cast<ConstantInt>(SI->getOperand(1))) {
@@ -2236,7 +2236,7 @@ static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
   return false;
 }
 
-/// emitBitfieldInsert - turn a shift used only by an and with immediate into 
+/// emitBitfieldInsert - turn a shift used only by an and with immediate into
 /// the rotate left word immediate then mask insert (rlwimi) instruction.
 /// Patterns matched:
 /// 1. or shl, and   5. or (shl-and), and   9. or and, and
@@ -2261,7 +2261,7 @@ bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
         matched = true;
       else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
         matched = true;
-  
+
   // Look for cases 1, 3, 5, and 7.  Force the shift argument to be the one
   // inserted into the target, since rlwimi can only rotate the value inserted,
   // not the value being inserted into.
@@ -2271,11 +2271,11 @@ bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
         std::swap(Op0User, Op1User);
         matched = true;
       }
-  
+
   // We didn't succeed in matching one of the patterns, so return false
   if (matched == false)
     return false;
-  
+
   // If the masks xor to -1, and the insert mask is a run of ones, then we have
   // succeeded in matching one of the cases for generating rlwimi.  Update the
   // skip lists and users of the Instruction::Or.
@@ -2284,7 +2284,7 @@ bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
     SkipList.push_back(Op0User);
     SkipList.push_back(Op1User);
     SkipList.push_back(OptAndI);
-    InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0), 
+    InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
                                Amount, MB, ME);
     return true;
   }
@@ -2293,7 +2293,7 @@ bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
 
 /// emitBitfieldExtract - turn a shift used only by an and with immediate into the
 /// rotate left word immediate then and with mask (rlwinm) instruction.
-bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB, 
+bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator IP,
                                     User *OpUser, unsigned DestReg) {
   return false;
@@ -2311,11 +2311,11 @@ bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
   if (isExtractShiftHalf)
     if (isExtractAndHalf)
       matched = true;
-  
+
   if (matched == false && isExtractAndHalf)
     if (isExtractShiftHalf)
     matched = true;
-  
+
   if (matched == false)
     return false;
 
@@ -2331,12 +2331,12 @@ bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
 }
 
 /// emitBinaryConstOperation - Implement simple binary operators for integral
-/// types with a constant operand.  Opcode is one of: 0 for Add, 1 for Sub, 
+/// types with a constant operand.  Opcode is one of: 0 for Add, 1 for Sub,
 /// 2 for And, 3 for Or, 4 for Xor, and 5 for Subtract-From.
 ///
-void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB, 
+void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
                                          MachineBasicBlock::iterator IP,
-                                         unsigned Op0Reg, ConstantInt *Op1, 
+                                         unsigned Op0Reg, ConstantInt *Op1,
                                          unsigned Opcode, unsigned DestReg) {
   static const unsigned OpTab[] = {
     PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR, PPC::SUBF
@@ -2351,13 +2351,13 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
     Op1 = cast<ConstantInt>(ConstantExpr::getNeg(Op1));
     Opcode = 0;
   }
-  
+
   // xor X, -1 -> not X
   if (Opcode == 4 && Op1->isAllOnesValue()) {
     BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
     return;
   }
-  
+
   if (Opcode == 2 && !Op1->isNullValue()) {
     unsigned MB, ME, mask = Op1->getRawValue();
     if (isRunOfOnes(mask, MB, ME)) {
@@ -2375,7 +2375,7 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
   bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
 
   // For Add, Sub, and SubF the instruction takes a signed immediate.  For And,
-  // Or, and Xor, the instruction takes an unsigned immediate.  There is no 
+  // Or, and Xor, the instruction takes an unsigned immediate.  There is no
   // shifted immediate form of SubF so disallow its opcode for those constants.
   if (canUseAsImmediateForOpcode(Op1, Opcode, false)) {
     if (Opcode < 2 || Opcode == 5)
@@ -2416,9 +2416,9 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
 ///
 void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
                                           MachineBasicBlock::iterator IP,
-                                          BinaryOperator *BO, 
+                                          BinaryOperator *BO,
                                           Value *Op0, Value *Op1,
-                                          unsigned OperatorClass, 
+                                          unsigned OperatorClass,
                                           unsigned DestReg) {
   // Arithmetic and Bitwise operators
   static const unsigned OpcodeTab[] = {
@@ -2428,7 +2428,7 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
     { PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
     { PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
   };
-  
+
   unsigned Class = getClassB(Op0->getType());
 
   if (Class == cFP32 || Class == cFP64) {
@@ -2466,7 +2466,7 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
     if (Class != cLong) {
       if (emitBitfieldInsert(BO, DestReg))
         return;
-      
+
       unsigned Op0r = getReg(Op0, MBB, IP);
       emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
       return;
@@ -2508,10 +2508,10 @@ void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
                            unsigned DestReg, Value *Op0, Value *Op1) {
   unsigned Class0 = getClass(Op0->getType());
   unsigned Class1 = getClass(Op1->getType());
-  
+
   unsigned Op0r = getReg(Op0, MBB, IP);
   unsigned Op1r = getReg(Op1, MBB, IP);
-  
+
   // 64 x 64 -> 64
   if (Class0 == cLong && Class1 == cLong) {
     unsigned Tmp1 = makeAnotherReg(Type::IntTy);
@@ -2526,7 +2526,7 @@ void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
     BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
     return;
   }
-  
+
   // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
   if (Class0 == cLong && Class1 <= cInt) {
     unsigned Tmp0 = makeAnotherReg(Type::IntTy);
@@ -2546,13 +2546,13 @@ void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
     BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
     return;
   }
-  
+
   // 32 x 32 -> 32
   if (Class0 <= cInt && Class1 <= cInt) {
     BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
     return;
   }
-  
+
   assert(0 && "doMultiply cannot operate on unknown type!");
 }
 
@@ -2570,7 +2570,7 @@ void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
       BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
     return;
   }
-  
+
   // Mul op0, 1 ==> op0
   if (CI->equalsInt(1)) {
     unsigned Op0r = getReg(Op0, MBB, IP);
@@ -2586,7 +2586,7 @@ void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
     emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), 0, DestReg);
     return;
   }
-  
+
   // If 32 bits or less and immediate is in right range, emit mul by immediate
   if (Class == cByte || Class == cShort || Class == cInt) {
     if (canUseAsImmediateForOpcode(CI, 0, false)) {
@@ -2596,7 +2596,7 @@ void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
       return;
     }
   }
-  
+
   doMultiply(MBB, IP, DestReg, Op0, CI);
 }
 
@@ -2678,7 +2678,7 @@ void PPC32ISel::emitDivRemOperation(MachineBasicBlock *MBB,
       // Floating point divide...
       emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
       return;
-    } else {               
+    } else {
       // Floating point remainder via fmod(double x, double y);
       unsigned Op0Reg = getReg(Op0, MBB, IP);
       unsigned Op1Reg = getReg(Op1, MBB, IP);
@@ -2732,7 +2732,7 @@ void PPC32ISel::emitDivRemOperation(MachineBasicBlock *MBB,
       if (log2V != 0 && Ty->isSigned()) {
         unsigned Op0Reg = getReg(Op0, MBB, IP);
         unsigned TmpReg = makeAnotherReg(Op0->getType());
-        
+
         BuildMI(*MBB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
         BuildMI(*MBB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
         return;
@@ -2783,12 +2783,12 @@ void PPC32ISel::visitShiftInst(ShiftInst &I) {
 ///
 void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
                                    MachineBasicBlock::iterator IP,
-                                   Value *Op, Value *ShiftAmount, 
+                                   Value *Op, Value *ShiftAmount,
                                    bool isLeftShift, const Type *ResultTy,
                                    ShiftInst *SI, unsigned DestReg) {
   bool isSigned = ResultTy->isSigned ();
   unsigned Class = getClass (ResultTy);
-  
+
   // Longs, as usual, are handled specially...
   if (Class == cLong) {
     unsigned SrcReg = getReg (Op, MBB, IP);
@@ -2861,7 +2861,7 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
       unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
       unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
       unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
-      
+
       if (isLeftShift) {
         BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
           .addSImm(32);
@@ -2879,7 +2879,7 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
         BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
           .addReg(ShiftAmountReg);
       } else {
-        if (isSigned) { // shift right algebraic 
+        if (isSigned) { // shift right algebraic
           MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
           MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
           MachineBasicBlock *OldMBB = BB;
@@ -2904,14 +2904,14 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
           BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
             .addReg(ShiftAmountReg);
           BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
- 
+
           // OrMBB:
           //   Select correct least significant half if the shift amount > 32
           BB = TmpMBB;
           unsigned OrReg = makeAnotherReg(Type::IntTy);
           BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addReg(TmpReg6);
           TmpMBB->addSuccessor(PhiMBB);
-          
+
           BB = PhiMBB;
           BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
             .addReg(OrReg).addMBB(TmpMBB);
@@ -2942,12 +2942,12 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
     // The shift amount is constant, guaranteed to be a ubyte. Get its value.
     assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
     unsigned Amount = CUI->getValue();
-    
+
     // If this is a shift with one use, and that use is an And instruction,
     // then attempt to emit a bitfield operation.
     if (SI && emitBitfieldInsert(SI, DestReg))
       return;
-    
+
     unsigned SrcReg = getReg (Op, MBB, IP);
     if (Amount == 0) {
       BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
@@ -3008,8 +3008,8 @@ static bool LoadNeedsSignExtend(LoadInst &LI) {
 ///
 void PPC32ISel::visitLoadInst(LoadInst &I) {
   // Immediate opcodes, for reg+imm addressing
-  static const unsigned ImmOpcodes[] = { 
-    PPC::LBZ, PPC::LHZ, PPC::LWZ, 
+  static const unsigned ImmOpcodes[] = {
+    PPC::LBZ, PPC::LHZ, PPC::LWZ,
     PPC::LFS, PPC::LFD, PPC::LWZ
   };
   // Indexed opcodes, for reg+reg addressing
@@ -3023,7 +3023,7 @@ void PPC32ISel::visitLoadInst(LoadInst &I) {
   unsigned IdxOpcode = IdxOpcodes[Class];
   unsigned DestReg   = getReg(I);
   Value *SourceAddr  = I.getOperand(0);
-  
+
   if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
   if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
 
@@ -3043,7 +3043,7 @@ void PPC32ISel::visitLoadInst(LoadInst &I) {
     }
     return;
   }
-  
+
   // If the offset fits in 16 bits, we can emit a reg+imm load, otherwise, we
   // use the index from the FoldedGEP struct and use reg+reg addressing.
   if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
@@ -3073,11 +3073,11 @@ void PPC32ISel::visitLoadInst(LoadInst &I) {
     }
     return;
   }
-  
+
   // The fallback case, where the load was from a source that could not be
-  // folded into the load instruction. 
+  // folded into the load instruction.
   unsigned SrcAddrReg = getReg(SourceAddr);
-    
+
   if (Class == cLong) {
     BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
     BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
@@ -3095,15 +3095,15 @@ void PPC32ISel::visitLoadInst(LoadInst &I) {
 void PPC32ISel::visitStoreInst(StoreInst &I) {
   // Immediate opcodes, for reg+imm addressing
   static const unsigned ImmOpcodes[] = {
-    PPC::STB, PPC::STH, PPC::STW, 
+    PPC::STB, PPC::STH, PPC::STW,
     PPC::STFS, PPC::STFD, PPC::STW
   };
   // Indexed opcodes, for reg+reg addressing
   static const unsigned IdxOpcodes[] = {
-    PPC::STBX, PPC::STHX, PPC::STWX, 
+    PPC::STBX, PPC::STHX, PPC::STWX,
     PPC::STFSX, PPC::STFDX, PPC::STWX
   };
-  
+
   Value *SourceAddr  = I.getOperand(1);
   const Type *ValTy  = I.getOperand(0)->getType();
   unsigned Class     = getClassB(ValTy);
@@ -3120,7 +3120,7 @@ void PPC32ISel::visitStoreInst(StoreInst &I) {
       addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
     return;
   }
-  
+
   // If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
   // use the index from the FoldedGEP struct and use reg+reg addressing.
   if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
@@ -3129,7 +3129,7 @@ void PPC32ISel::visitStoreInst(StoreInst &I) {
     unsigned baseReg = GEPMap[GEPI].base;
     unsigned indexReg = GEPMap[GEPI].index;
     ConstantSInt *offset = GEPMap[GEPI].offset;
-    
+
     if (Class != cLong) {
       if (indexReg == 0)
         BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
@@ -3147,7 +3147,7 @@ void PPC32ISel::visitStoreInst(StoreInst &I) {
     }
     return;
   }
-  
+
   // If the store address wasn't the only use of a GEP, we fall back to the
   // standard path: store the ValReg at the value in AddressReg.
   unsigned AddressReg  = getReg(I.getOperand(1));
@@ -3182,10 +3182,10 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
       if (!isa<GetElementPtrInst>(*I)) {
         AllUsesAreGEPs = false;
         break;
-      }        
+      }
     if (AllUsesAreGEPs) return;
   }
-  
+
   unsigned DestReg = getReg(CI);
   MachineBasicBlock::iterator MI = BB->end();
 
@@ -3198,7 +3198,7 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
     if (SI && (SI->getOperand(1) == &CI)) {
       unsigned SrcReg = getReg(Op, BB, MI);
       BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
-      return; 
+      return;
     }
   }
 
@@ -3212,13 +3212,13 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
       if (!isa<StoreInst>(*I)) {
         AllUsesAreStores = false;
         break;
-      }        
+      }
     // Turn this cast directly into a move instruction, which the register
     // allocator will deal with.
-    if (AllUsesAreStores) { 
+    if (AllUsesAreStores) {
       unsigned SrcReg = getReg(Op, BB, MI);
       BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
-      return; 
+      return;
     }
   }
   emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
@@ -3291,13 +3291,13 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
     BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
     return;
   }
-  
+
   // Handle cast of Double -> Float
   if (SrcClass == cFP64 && DestClass == cFP32) {
     BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
     return;
   }
-  
+
   // Handle casts from integer to floating point now...
   if (DestClass == cFP32 || DestClass == cFP64) {
 
@@ -3343,14 +3343,14 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
         doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
         BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
         BB->addSuccessor(PhiMBB);
-        
+
         // SetMBB
         BB = SetMBB;
         unsigned SetReg = makeAnotherReg(DestTy);
         unsigned CallReg = makeAnotherReg(DestTy);
         unsigned ShiftedReg = makeAnotherReg(SrcTy);
         ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
-        emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0, 
+        emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
                            ShiftedReg);
         SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
         TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
@@ -3358,7 +3358,7 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
         unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
         BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
         BB->addSuccessor(PhiMBB);
-        
+
         // PhiMBB
         BB = PhiMBB;
         BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
@@ -3366,14 +3366,14 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
       }
       return;
     }
-    
+
     // Make sure we're dealing with a full 32 bits
     if (SrcClass < cInt) {
       unsigned TmpReg = makeAnotherReg(Type::IntTy);
       promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
       SrcReg = TmpReg;
     }
-    
+
     // Spill the integer to memory and reload it from there.
     // Also spill room for a special conversion constant
     int ValueFrameIdx =
@@ -3381,14 +3381,14 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
 
     unsigned constantHi = makeAnotherReg(Type::IntTy);
     unsigned TempF = makeAnotherReg(Type::DoubleTy);
-    
+
     if (!SrcTy->isSigned()) {
       ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
       unsigned ConstF = getReg(CFP, BB, IP);
       BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
-      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi), 
+      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
                         ValueFrameIdx);
-      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg), 
+      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
                         ValueFrameIdx, 4);
       addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
       BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
@@ -3397,10 +3397,10 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
       unsigned ConstF = getReg(CFP, BB, IP);
       unsigned TempLo = makeAnotherReg(Type::IntTy);
       BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
-      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi), 
+      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
                         ValueFrameIdx);
       BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
-      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo), 
+      addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
                         ValueFrameIdx, 4);
       addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
       BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
@@ -3430,24 +3430,24 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
 
     if (DestTy->isSigned()) {
       unsigned TempReg = makeAnotherReg(Type::DoubleTy);
-      
+
       // Convert to integer in the FP reg and store it to a stack slot
       BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
       addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
                           .addReg(TempReg), ValueFrameIdx);
 
       // There is no load signed byte opcode, so we must emit a sign extend for
-      // that particular size.  Make sure to source the new integer from the 
+      // that particular size.  Make sure to source the new integer from the
       // correct offset.
       if (DestClass == cByte) {
         unsigned TempReg2 = makeAnotherReg(DestTy);
-        addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2), 
+        addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
                           ValueFrameIdx, 7);
         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
       } else {
         int offset = (DestClass == cShort) ? 6 : 4;
         unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
-        addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg), 
+        addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
                           ValueFrameIdx, offset);
       }
     } else {
@@ -3464,7 +3464,7 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
       unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
       unsigned IntTmp = makeAnotherReg(Type::IntTy);
       unsigned XorReg = makeAnotherReg(Type::IntTy);
-      int FrameIdx = 
+      int FrameIdx =
         F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
       // Update machine-CFG edges
       MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
@@ -3524,15 +3524,15 @@ void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
   }
 
   // Check our invariants
-  assert((SrcClass <= cInt || SrcClass == cLong) && 
+  assert((SrcClass <= cInt || SrcClass == cLong) &&
          "Unhandled source class for cast operation!");
-  assert((DestClass <= cInt || DestClass == cLong) && 
+  assert((DestClass <= cInt || DestClass == cLong) &&
          "Unhandled destination class for cast operation!");
 
   bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
   bool destUnsigned = DestTy->isUnsigned();
 
-  // Unsigned -> Unsigned, clear if larger, 
+  // Unsigned -> Unsigned, clear if larger,
   if (sourceUnsigned && destUnsigned) {
     // handle long dest class now to keep switch clean
     if (DestClass == cLong) {
@@ -3754,18 +3754,18 @@ void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
   // multiple definitions of the base register.
   if (GEPIsFolded && (GEPMap[GEPI].base != 0))
     return;
-  
+
   Value *Src = GEPI->getOperand(0);
   User::op_iterator IdxBegin = GEPI->op_begin()+1;
   User::op_iterator IdxEnd = GEPI->op_end();
   const TargetData &TD = TM.getTargetData();
   const Type *Ty = Src->getType();
   int32_t constValue = 0;
-  
+
   // Record the operations to emit the GEP in a vector so that we can emit them
   // after having analyzed the entire instruction.
   std::vector<CollapsedGepOp> ops;
-  
+
   // GEPs have zero or more indices; we must perform a struct access
   // or array access for each one.
   for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
@@ -3800,7 +3800,7 @@ void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
       // type is the type of the elements in the array).
       Ty = SqTy->getElementType();
       unsigned elementSize = TD.getTypeSize(Ty);
-      
+
       if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
         if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
           constValue += CS->getValue() * elementSize;
@@ -3833,15 +3833,15 @@ void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
       TmpReg1 = makeAnotherReg(Type::IntTy);
       doMultiplyConst(MBB, IP, TmpReg1, cgo.index, cgo.size);
     }
-    
+
     unsigned TmpReg2;
-    if (cgo.offset->isNullValue()) { 
+    if (cgo.offset->isNullValue()) {
       TmpReg2 = TmpReg1;
     } else {
       TmpReg2 = makeAnotherReg(Type::IntTy);
       emitBinaryConstOperation(MBB, IP, TmpReg1, cgo.offset, 0, TmpReg2);
     }
-    
+
     if (indexReg == 0)
       indexReg = TmpReg2;
     else {
@@ -3850,12 +3850,12 @@ void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
       indexReg = TmpReg3;
     }
   }
-  
+
   // We now have a base register, an index register, and possibly a constant
   // remainder.  If the GEP is going to be folded, we try to generate the
   // optimal addressing mode.
   ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
-  
+
   // If we are emitting this during a fold, copy the current base register to
   // the target, and save the current constant offset so the folding load or
   // store can try and use it as an immediate.
@@ -3904,7 +3904,7 @@ void PPC32ISel::visitAllocaInst(AllocaInst &I) {
   // statically stack allocate the space, so we don't need to do anything here.
   //
   if (dyn_castFixedAlloca(&I)) return;
-  
+
   // Find the data size of the alloca inst's getAllocatedType.
   const Type *Ty = I.getAllocatedType();
   unsigned TySize = TM.getTargetData().getTypeSize(Ty);
@@ -3912,7 +3912,7 @@ void PPC32ISel::visitAllocaInst(AllocaInst &I) {
   // Create a register to hold the temporary result of multiplying the type size
   // constant by the variable amount.
   unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
-  
+
   // TotalSizeReg = mul <numelements>, <TypeSize>
   MachineBasicBlock::iterator MBBI = BB->end();
   ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
@@ -3926,7 +3926,7 @@ void PPC32ISel::visitAllocaInst(AllocaInst &I) {
   unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
   BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
     .addImm(0).addImm(27);
-  
+
   // Subtract size from stack pointer, thereby allocating some space.
   BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(AlignedSize).addReg(PPC::R1);
 
@@ -3957,7 +3957,7 @@ void PPC32ISel::visitMallocInst(MallocInst &I) {
 
   std::vector<ValueRecord> Args;
   Args.push_back(ValueRecord(Arg, Type::UIntTy));
-  MachineInstr *TheCall = 
+  MachineInstr *TheCall =
     BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
   doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
 }
@@ -3968,11 +3968,11 @@ void PPC32ISel::visitMallocInst(MallocInst &I) {
 void PPC32ISel::visitFreeInst(FreeInst &I) {
   std::vector<ValueRecord> Args;
   Args.push_back(ValueRecord(I.getOperand(0)));
-  MachineInstr *TheCall = 
+  MachineInstr *TheCall =
     BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
   doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
 }
-   
+
 /// createPPC32ISelSimple - This pass converts an LLVM function into a machine
 /// code representation is a very simple peep-hole fashion.
 ///
diff --git a/lib/Target/PowerPC/PPC32JITInfo.h b/lib/Target/PowerPC/PPC32JITInfo.h
index 5fa0b58b4c..cbbfa9fc7c 100644
--- a/lib/Target/PowerPC/PPC32JITInfo.h
+++ b/lib/Target/PowerPC/PPC32JITInfo.h
@@ -1,10 +1,10 @@
 //===- PPC32JITInfo.h - PowerPC/Darwin JIT interface --------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetJITInfo class.
diff --git a/lib/Target/PowerPC/PPC64CodeEmitter.cpp b/lib/Target/PowerPC/PPC64CodeEmitter.cpp
index 06f422c3d5..6c438049f4 100644
--- a/lib/Target/PowerPC/PPC64CodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPC64CodeEmitter.cpp
@@ -1,12 +1,12 @@
 //===-- PPC64CodeEmitter.cpp - JIT Code Emitter for PPC64 -----*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 //
 //===----------------------------------------------------------------------===//
 
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 5604a9e8e5..e196a2bec6 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -4,7 +4,7 @@
 //
 // This file was developed by Nate Begeman and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a pattern matching instruction selector for 64 bit PowerPC.
@@ -45,7 +45,7 @@ namespace {
       addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);
       addRegisterClass(MVT::f64, PPC64::FPRCRegisterClass);
-      
+
       // PowerPC has no intrinsics for these particular operations
       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
@@ -62,7 +62,7 @@ namespace {
 
       setShiftAmountFlavor(Extend);   // shl X, 32 == 0
       addLegalFPImmediate(+0.0); // Necessary for FSEL
-      addLegalFPImmediate(-0.0); // 
+      addLegalFPImmediate(-0.0); //
 
       computeRegisterProperties();
     }
@@ -71,16 +71,16 @@ namespace {
     /// lower the arguments for the specified function, into the specified DAG.
     virtual std::vector<SDOperand>
     LowerArguments(Function &F, SelectionDAG &DAG);
-    
+
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
                 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand, SDOperand>
     LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand,SDOperand>
     LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
@@ -101,8 +101,8 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineBasicBlock& BB = MF.front();
   std::vector<SDOperand> ArgValues;
-  
-  // Due to the rather complicated nature of the PowerPC ABI, rather than a 
+
+  // Due to the rather complicated nature of the PowerPC ABI, rather than a
   // fixed size array of physical args, for the sake of simplicity let the STL
   // handle tracking them for us.
   std::vector<unsigned> argVR, argPR, argOp;
@@ -110,7 +110,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   unsigned GPR_remaining = 8;
   unsigned FPR_remaining = 13;
   unsigned GPR_idx = 0, FPR_idx = 0;
-  static const unsigned GPR[] = { 
+  static const unsigned GPR[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
@@ -126,13 +126,13 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     SDOperand newroot, argt;
     bool needsLoad = false;
     MVT::ValueType ObjectVT = getValueType(I->getType());
-    
+
     switch (ObjectVT) {
     default: assert(0 && "Unhandled argument type!");
     case MVT::i1:
     case MVT::i8:
     case MVT::i16:
-    case MVT::i32: 
+    case MVT::i32:
     case MVT::i64:
       if (GPR_remaining > 0) {
         BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
@@ -148,7 +148,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     case MVT::f64:
       if (FPR_remaining > 0) {
         BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
-        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT, 
+        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
                                             DAG.getRoot());
         --FPR_remaining;
         ++FPR_idx;
@@ -157,9 +157,9 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       }
       break;
     }
-    
+
     // We need to load the argument to a virtual register if we determined above
-    // that we ran out of physical registers of the appropriate type 
+    // that we ran out of physical registers of the appropriate type
     if (needsLoad) {
       unsigned SubregOffset = 0;
       switch (ObjectVT) {
@@ -167,18 +167,18 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       case MVT::i1:
       case MVT::i8:   SubregOffset = 7; break;
       case MVT::i16:  SubregOffset = 6; break;
-      case MVT::i32: 
+      case MVT::i32:
       case MVT::f32:  SubregOffset = 4; break;
-      case MVT::i64:  
+      case MVT::i64:
       case MVT::f64:  SubregOffset = 0; break;
       }
       int FI = MFI->CreateFixedObject(8, ArgOffset);
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
-      FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN, 
+      FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
                         DAG.getConstant(SubregOffset, MVT::i64));
       argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
     }
-    
+
     // Every 4 bytes of argument space consumes one of the GPRs available for
     // argument passing.
     if (GPR_remaining > 0) {
@@ -186,7 +186,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       ++GPR_idx;
     }
     ArgOffset += 8;
-    
+
     DAG.setRoot(newroot.getValue(1));
     ArgValues.push_back(argt);
   }
@@ -203,7 +203,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
       BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
-      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 
+      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                     Val, FIN);
       MemOps.push_back(Store);
       // Increment the address by eight for the next argument to store
@@ -233,8 +233,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
                         DAG.getConstant(NumBytes, getPointerTy()));
   } else {
     NumBytes = 8 * Args.size(); // All arguments are rounded up to 8 bytes
-    
-    // Just to be safe, we'll always reserve the full 48 bytes of linkage area 
+
+    // Just to be safe, we'll always reserve the full 48 bytes of linkage area
     // plus 64 bytes of argument space in case any called code gets funky on us.
     if (NumBytes < 112) NumBytes = 112;
 
@@ -248,7 +248,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
     // passing.
     SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
                                             DAG.getEntryNode());
-    
+
     // Figure out which arguments are going to go in registers, and which in
     // memory.  Also, if this is a vararg function, floating point operations
     // must be stored to our stack, and loaded into integer regs as well, if
@@ -256,7 +256,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
     unsigned ArgOffset = 48;
     unsigned GPR_remaining = 8;
     unsigned FPR_remaining = 13;
-    
+
     std::vector<SDOperand> MemOps;
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
       // PtrOff will be used to store the current argument to the stack if a
@@ -264,7 +264,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
       MVT::ValueType ArgVT = getValueType(Args[i].second);
-      
+
       switch (ArgVT) {
       default: assert(0 && "Unexpected ValueType for argument!");
       case MVT::i1:
@@ -323,14 +323,14 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
     if (!MemOps.empty())
       Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
   }
-  
+
   std::vector<MVT::ValueType> RetVals;
   MVT::ValueType RetTyVT = getValueType(RetTy);
   if (RetTyVT != MVT::isVoid)
     RetVals.push_back(RetTyVT);
   RetVals.push_back(MVT::Other);
 
-  SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 
+  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
                                             Chain, Callee, args_to_use), 0);
   Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
   Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
@@ -357,7 +357,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   }
   return std::make_pair(Result, Chain);
 }
-               
+
 
 std::pair<SDOperand, SDOperand> PPC64TargetLowering::
 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
@@ -374,10 +374,10 @@ Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
 /// SelectionDAG operations.
 //===--------------------------------------------------------------------===//
 class ISel : public SelectionDAGISel {
-  
+
   /// Comment Here.
   PPC64TargetLowering PPC64Lowering;
-  
+
   /// ExprMap - As shared expressions are codegen'd, we keep track of which
   /// vreg the value is produced in, so we only emit one copy of each compiled
   /// tree.
@@ -385,37 +385,37 @@ class ISel : public SelectionDAGISel {
 
   unsigned GlobalBaseReg;
   bool GlobalBaseInitialized;
-  
+
 public:
-  ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM) 
+  ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
   {}
-  
+
   /// runOnFunction - Override this function in order to reset our per-function
   /// variables.
   virtual bool runOnFunction(Function &Fn) {
     // Make sure we re-emit a set of the global base reg if necessary
     GlobalBaseInitialized = false;
     return SelectionDAGISel::runOnFunction(Fn);
-  } 
-  
+  }
+
   /// InstructionSelectBasicBlock - This callback is invoked by
   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
     DEBUG(BB->dump());
     // Codegen the basic block.
     Select(DAG.getRoot());
-    
+
     // Clear state used for selection.
     ExprMap.clear();
   }
-  
+
   unsigned getGlobalBaseReg();
   unsigned getConstDouble(double floatVal, unsigned Result);
   unsigned SelectSetCR0(SDOperand CC);
   unsigned SelectExpr(SDOperand N);
   unsigned SelectExprFP(SDOperand N, unsigned Result);
   void Select(SDOperand N);
-  
+
   bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
   void SelectBranchCC(SDOperand N);
 };
@@ -435,7 +435,7 @@ static unsigned ExactLog2(unsigned Val) {
 /// getImmediateForOpcode - This method returns a value indicating whether
 /// the ConstantSDNode N can be used as an immediate to Opcode.  The return
 /// values are either 0, 1 or 2.  0 indicates that either N is not a
-/// ConstantSDNode, or is not suitable for use by that opcode.  A return value 
+/// ConstantSDNode, or is not suitable for use by that opcode.  A return value
 /// of 1 indicates that the constant may be used in normal immediate form.  A
 /// return value of 2 indicates that the constant may be used in shifted
 /// immediate form.  A return value of 3 indicates that log base 2 of the
@@ -446,7 +446,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
   if (N.getOpcode() != ISD::Constant) return 0;
 
   int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-  
+
   switch(Opcode) {
   default: return 0;
   case ISD::ADD:
@@ -528,7 +528,7 @@ unsigned ISel::getGlobalBaseReg() {
   return GlobalBaseReg;
 }
 
-/// getConstDouble - Loads a floating point value into a register, via the 
+/// getConstDouble - Loads a floating point value into a register, via the
 /// Constant Pool.  Optionally takes a register in which to load the value.
 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
   unsigned Tmp1 = MakeReg(MVT::i64);
@@ -544,9 +544,9 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
 
 unsigned ISel::SelectSetCR0(SDOperand CC) {
   unsigned Opc, Tmp1, Tmp2;
-  static const unsigned CompareOpcodes[] = 
+  static const unsigned CompareOpcodes[] =
     { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-  
+
   // If the first operand to the select is a SETCC node, then we can fold it
   // into the branch that selects which value to return.
   SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
@@ -557,7 +557,7 @@ unsigned ISel::SelectSetCR0(SDOperand CC) {
 
     // Pass the optional argument U to getImmediateForOpcode for SETCC,
     // so that it knows whether the SETCC immediate range is signed or not.
-    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC, 
+    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
                                    Tmp2, U)) {
       if (U)
         BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
@@ -586,7 +586,7 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
       offset = imm;
       return false;
-    } 
+    }
     offset = SelectExpr(N.getOperand(1));
     return true;
   }
@@ -598,14 +598,14 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
 void ISel::SelectBranchCC(SDOperand N)
 {
   assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
-  MachineBasicBlock *Dest = 
+  MachineBasicBlock *Dest =
     cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
 
   // Get the MBB we will fall through to so that we can hand it off to the
   // branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
   //ilist<MachineBasicBlock>::iterator It = BB;
   //MachineBasicBlock *Fallthrough = ++It;
-  
+
   Select(N.getOperand(0));  //chain
   unsigned Opc = SelectSetCR0(N.getOperand(1));
   // FIXME: Use this once we have something approximating two-way branches
@@ -645,7 +645,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
       unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
       unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-      
+
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
       if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
         switch(SetCC->getCondition()) {
@@ -704,12 +704,12 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       assert(0 && "Should never get here");
       return 0;
     }
-    
+
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     Opc = SelectSetCR0(N.getOperand(0));
 
-    // Create an iterator with which to insert the MBB for copying the false 
+    // Create an iterator with which to insert the MBB for copying the false
     // value and the MBB to hold the PHI instruction for this SetCC.
     MachineBasicBlock *thisMBB = BB;
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -749,7 +749,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
   }
 
   case ISD::FNEG:
-    if (!NoExcessFPPrecision && 
+    if (!NoExcessFPPrecision &&
         ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -760,7 +760,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
       Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-    } else if (!NoExcessFPPrecision && 
+    } else if (!NoExcessFPPrecision &&
         ISD::SUB == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -779,23 +779,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::FABS:
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_ROUND:
-    assert (DestType == MVT::f32 && 
-            N.getOperand(0).getValueType() == MVT::f64 && 
+    assert (DestType == MVT::f32 &&
+            N.getOperand(0).getValueType() == MVT::f64 &&
             "only f64 to f32 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_EXTEND:
-    assert (DestType == MVT::f64 && 
-            N.getOperand(0).getValueType() == MVT::f32 && 
+    assert (DestType == MVT::f64 &&
+            N.getOperand(0).getValueType() == MVT::f32 &&
             "only f32 to f64 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
@@ -807,13 +807,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
     Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
     return Result;
-    
+
   case ISD::ConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     Result = getConstDouble(CN->getValue(), Result);
     return Result;
   }
-    
+
   case ISD::ADD:
     if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
         N.getOperand(0).Val->hasOneUse()) {
@@ -866,10 +866,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
     Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
     Tmp3 = MakeReg(MVT::i64); // temp reg to hold the conversion constant
     unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
-    
+
     int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
     MachineConstantPool *CP = BB->getParent()->getConstantPool();
-    
+
     // FIXME: pull this FP constant generation stuff out into something like
     // the simple ISel's getReg.
     if (IsUnsigned) {
@@ -935,7 +935,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
 
   if (ISD::CopyFromReg == opcode)
     DestType = N.getValue(0).getValueType();
-    
+
   if (DestType == MVT::f64 || DestType == MVT::f32)
     if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
       return SelectExprFP(N, Result);
@@ -983,7 +983,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
     addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
     return Result;
-  
+
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     Tmp1 = MakeReg(MVT::i64);
@@ -1004,7 +1004,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
       Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
     bool sext = (ISD::SEXTLOAD == opcode);
-    
+
     // Make sure we generate both values.
     if (Result != 1)
       ExprMap[N.getValue(1)] = 1;   // Generate the token
@@ -1025,7 +1025,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     case MVT::f32: Opc = PPC::LFS; break;
     case MVT::f64: Opc = PPC::LFD; break;
     }
-    
+
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
       Tmp1 = MakeReg(MVT::i64);
       int CPI = CP->getIndex();
@@ -1048,10 +1048,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
     }
     return Result;
   }
-    
+
   case ISD::CALL: {
     unsigned GPR_idx = 0, FPR_idx = 0;
-    static const unsigned GPR[] = { 
+    static const unsigned GPR[] = {
       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
@@ -1066,13 +1066,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
 
     MachineInstr *CallMI;
     // Emit the correct call instruction based on the type of symbol called.
-    if (GlobalAddressSDNode *GASD = 
+    if (GlobalAddressSDNode *GASD =
         dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
                                                            true);
-    } else if (ExternalSymbolSDNode *ESSDN = 
+    } else if (ExternalSymbolSDNode *ESSDN =
                dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
                                                             true);
     } else {
       Tmp1 = SelectExpr(N.getOperand(1));
@@ -1081,7 +1081,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
         .addReg(PPC::R12);
     }
-       
+
     // Load the register args to virtual regs
     std::vector<unsigned> ArgVR;
     for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
@@ -1112,7 +1112,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
         break;
       }
     }
-    
+
     // Put the call instruction in the correct place in the MachineBasicBlock
     BB->push_back(CallMI);
 
@@ -1140,20 +1140,20 @@ unsigned ISel::SelectExpr(SDOperand N) {
     switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i32:
-      BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
       break;
     case MVT::i16:
-      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
       break;
     case MVT::i8:
-      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
       break;
     case MVT::i1:
       BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
       break;
     }
     return Result;
-    
+
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
@@ -1172,7 +1172,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       BuildMI(BB, PPC::SLD, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1184,7 +1184,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       BuildMI(BB, PPC::SRD, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRA:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1195,7 +1195,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       BuildMI(BB, PPC::SRAD, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-  
+
   case ISD::ADD:
     Tmp1 = SelectExpr(N.getOperand(0));
     switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
@@ -1302,7 +1302,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::MUL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
@@ -1338,23 +1338,23 @@ unsigned ISel::SelectExpr(SDOperand N) {
     addFrameReference(BuildMI(BB, PPC::LD, 2, Result), FrameIdx);
     return Result;
   }
- 
+
   case ISD::SETCC:
     if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
       Opc = SelectSetCR0(N);
-      
+
       unsigned TrueValue = MakeReg(MVT::i32);
       BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
       unsigned FalseValue = MakeReg(MVT::i32);
       BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
 
-      // Create an iterator with which to insert the MBB for copying the false 
+      // Create an iterator with which to insert the MBB for copying the false
       // value and the MBB to hold the PHI instruction for this SetCC.
       MachineBasicBlock *thisMBB = BB;
       const BasicBlock *LLVM_BB = BB->getBasicBlock();
       ilist<MachineBasicBlock>::iterator It = BB;
       ++It;
-  
+
       //  thisMBB:
       //  ...
       //   cmpTY cr0, r1, r2
@@ -1387,13 +1387,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
     }
     assert(0 && "Is this legal?");
     return 0;
-    
+
   case ISD::SELECT: {
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     Opc = SelectSetCR0(N.getOperand(0));
 
-    // Create an iterator with which to insert the MBB for copying the false 
+    // Create an iterator with which to insert the MBB for copying the false
     // value and the MBB to hold the PHI instruction for this SetCC.
     MachineBasicBlock *thisMBB = BB;
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1467,7 +1467,7 @@ void ISel::Select(SDOperand N) {
     return;  // Already selected.
 
   SDNode *Node = N.Val;
-  
+
   switch (Node->getOpcode()) {
   default:
     Node->dump(); std::cerr << "\n";
@@ -1492,16 +1492,16 @@ void ISel::Select(SDOperand N) {
     BuildMI(BB, PPC::B, 1).addMBB(Dest);
     return;
   }
-  case ISD::BRCOND: 
+  case ISD::BRCOND:
     SelectBranchCC(N);
     return;
   case ISD::CopyToReg:
     Select(N.getOperand(0));
     Tmp1 = SelectExpr(N.getOperand(1));
     Tmp2 = cast<RegSDNode>(N)->getReg();
-    
+
     if (Tmp1 != Tmp2) {
-      if (N.getOperand(1).getValueType() == MVT::f64 || 
+      if (N.getOperand(1).getValueType() == MVT::f64 ||
           N.getOperand(1).getValueType() == MVT::f32)
         BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
       else
@@ -1546,8 +1546,8 @@ void ISel::Select(SDOperand N) {
     }
     BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
     return;
-  case ISD::TRUNCSTORE: 
-  case ISD::STORE: 
+  case ISD::TRUNCSTORE:
+  case ISD::STORE:
     {
       SDOperand Chain   = N.getOperand(0);
       SDOperand Value   = N.getOperand(1);
@@ -1582,7 +1582,7 @@ void ISel::Select(SDOperand N) {
       {
         int offset;
         bool idx = SelectAddr(Address, Tmp2, offset);
-        if (idx) { 
+        if (idx) {
           Opc = IndexedOpForOp(Opc);
           BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
         } else {
@@ -1611,6 +1611,6 @@ void ISel::Select(SDOperand N) {
 /// description file.
 ///
 FunctionPass *llvm::createPPC64ISelPattern(TargetMachine &TM) {
-  return new ISel(TM);  
+  return new ISel(TM);
 }
 
diff --git a/lib/Target/PowerPC/PPC64InstrInfo.cpp b/lib/Target/PowerPC/PPC64InstrInfo.cpp
index 3a68ad66d0..929f5d1e60 100644
--- a/lib/Target/PowerPC/PPC64InstrInfo.cpp
+++ b/lib/Target/PowerPC/PPC64InstrInfo.cpp
@@ -1,10 +1,10 @@
 //===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetInstrInfo class.
diff --git a/lib/Target/PowerPC/PPC64InstrInfo.h b/lib/Target/PowerPC/PPC64InstrInfo.h
index ad05a540a8..e2e643c56d 100644
--- a/lib/Target/PowerPC/PPC64InstrInfo.h
+++ b/lib/Target/PowerPC/PPC64InstrInfo.h
@@ -1,10 +1,10 @@
 //===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC64 implementation of the TargetInstrInfo class.
@@ -47,7 +47,7 @@ public:
     case PPC::BGE: return PPC::BLT;
     case PPC::BGT: return PPC::BLE;
     case PPC::BLE: return PPC::BGT;
-    } 
+    }
   }
 };
 
diff --git a/lib/Target/PowerPC/PPC64JITInfo.h b/lib/Target/PowerPC/PPC64JITInfo.h
index 06ecffe846..9e994c26b6 100644
--- a/lib/Target/PowerPC/PPC64JITInfo.h
+++ b/lib/Target/PowerPC/PPC64JITInfo.h
@@ -1,10 +1,10 @@
 //===- PPC64JITInfo.h - PowerPC/AIX impl. of the JIT interface -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC/AIX implementation of the TargetJITInfo class.
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
index 0ff039438c..46f0e1cc0e 100644
--- a/lib/Target/PowerPC/PPC64RegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
@@ -1,10 +1,10 @@
 //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC64 implementation of the MRegisterInfo class.
@@ -38,7 +38,7 @@ namespace llvm {
 
 PPC64RegisterInfo::PPC64RegisterInfo()
   : PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
-  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;    
+  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
@@ -62,7 +62,7 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
       case 1:  return 0;
       case 2:  return 1;
       case 4:  return 2;
-      case 8:  return 3;         
+      case 8:  return 3;
     }
   } else if (RC == PPC64::FPRCRegisterClass) {
     switch (RC->getSize()) {
@@ -75,12 +75,12 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
   abort();
 }
 
-void 
+void
 PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  static const unsigned Opcode[] = { 
-    PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
+  static const unsigned Opcode[] = {
+    PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
   };
   unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
@@ -97,8 +97,8 @@ void
 PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx) const{
-  static const unsigned Opcode[] = { 
-    PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD 
+  static const unsigned Opcode[] = {
+    PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
   };
   unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
@@ -121,7 +121,7 @@ void PPC64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
     BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == PPC64::FPRCRegisterClass) {
     BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
-  } else { 
+  } else {
     std::cerr << "Attempt to copy register that is not GPR or FPR";
     abort();
   }
@@ -155,7 +155,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       // alignment boundary.
       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
       Amount = (Amount+Align-1)/Align*Align;
-      
+
       // Replace the pseudo instruction with a new instruction...
       if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
         MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
@@ -176,7 +176,7 @@ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
-  
+
   while (!MI.getOperand(i).isFrameIndex()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -198,7 +198,7 @@ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   // SP before having the stack size subtracted from it, then add the stack size
   // to Offset to get the correct offset.
   Offset += MF.getFrameInfo()->getStackSize();
-  
+
   if (Offset > 32767 || Offset < -32768) {
     // Insert a set of r0 with the full offset value before the ld, st, or add
     MachineBasicBlock *MBB = MI.getParent();
@@ -208,7 +208,7 @@ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     // convert into indexed form of the instruction
     // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
     // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
-    unsigned NewOpcode = 
+    unsigned NewOpcode =
       const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
     assert(NewOpcode && "No indexed form of load or store available!");
     MI.setOpcode(NewOpcode);
@@ -226,15 +226,15 @@ void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineInstr *MI;
-  
+
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI->getStackSize();
 
   // If we have calls, we cannot use the red zone to store callee save registers
   // and we must set up a stack frame, so calculate the necessary size here.
   if (MFI->hasCalls()) {
-    // We reserve argument space for call sites in the function immediately on 
-    // entry to the current function.  This eliminates the need for add/sub 
+    // We reserve argument space for call sites in the function immediately on
+    // entry to the current function.  This eliminates the need for add/sub
     // brackets around call sites.
     NumBytes += MFI->getMaxCallFrameSize();
   }
@@ -242,7 +242,7 @@ void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
   // Do we need to allocate space on the stack?
   if (NumBytes == 0) return;
 
-  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom 
+  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom
   // of the stack and round the size to a multiple of the alignment.
   unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
   unsigned GPRSize = getSpillSize(PPC::R1)/8;
@@ -266,7 +266,7 @@ void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
     MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
     MBB.insert(MBBI, MI);
   }
-  
+
   if (hasFP(MF)) {
     MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
     MBB.insert(MBBI, MI);
@@ -282,7 +282,7 @@ void PPC64RegisterInfo::emitEpilogue(MachineFunction &MF,
   MachineInstr *MI;
   assert(MBBI->getOpcode() == PPC::BLR &&
          "Can only insert epilog into returning blocks");
-  
+
   // Get the number of bytes allocated from the FrameInfo...
   unsigned NumBytes = MFI->getStackSize();
 
@@ -314,7 +314,7 @@ PPC64RegisterInfo::getRegClassForType(const Type* Ty) const {
     case Type::PointerTyID:
     case Type::LongTyID:
     case Type::ULongTyID:  return &GPRCInstance;
-     
+
     case Type::FloatTyID:
     case Type::DoubleTyID: return &FPRCInstance;
   }
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.h b/lib/Target/PowerPC/PPC64RegisterInfo.h
index 31fd0e6559..0580dc7609 100644
--- a/lib/Target/PowerPC/PPC64RegisterInfo.h
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.h
@@ -1,10 +1,10 @@
 //===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the MRegisterInfo class.
@@ -36,7 +36,7 @@ public:
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIndex) const;
-  
+
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
diff --git a/lib/Target/PowerPC/PPC64TargetMachine.h b/lib/Target/PowerPC/PPC64TargetMachine.h
index 587d1552f7..6d35527b1f 100644
--- a/lib/Target/PowerPC/PPC64TargetMachine.h
+++ b/lib/Target/PowerPC/PPC64TargetMachine.h
@@ -1,12 +1,12 @@
 //===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the PowerPC specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 4acaca7b51..80a59d751b 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1,10 +1,10 @@
 //===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
@@ -45,14 +45,14 @@ namespace {
   struct PowerPCAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
     std::set<std::string> Strings;
-    
+
     PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
       : AsmPrinter(O, TM), LabelNumber(0) {}
 
     /// Unique incrementer for label values for referencing Global values.
     ///
     unsigned LabelNumber;
-  
+
     virtual const char *getPassName() const {
       return "PowerPC Assembly Printer";
     }
@@ -109,7 +109,7 @@ namespace {
       if (MI->getOperand(OpNo).isImmediate()) {
         O << "$+" << MI->getOperand(OpNo).getImmedValue();
       } else {
-        printOp(MI->getOperand(OpNo), 
+        printOp(MI->getOperand(OpNo),
                 TM.getInstrInfo()->isCall(MI->getOpcode()));
       }
     }
@@ -158,12 +158,12 @@ namespace {
       }
       O << 4 * RegNo + value;
     }
-  
+
     virtual void printConstantPool(MachineConstantPool *MCP) = 0;
-    virtual bool runOnMachineFunction(MachineFunction &F) = 0;    
+    virtual bool runOnMachineFunction(MachineFunction &F) = 0;
     virtual bool doFinalization(Module &M) = 0;
   };
-  
+
   /// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
   /// X
   ///
@@ -183,10 +183,10 @@ namespace {
     }
 
     void printConstantPool(MachineConstantPool *MCP);
-    bool runOnMachineFunction(MachineFunction &F);    
+    bool runOnMachineFunction(MachineFunction &F);
     bool doFinalization(Module &M);
   };
-  
+
   /// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
   ///
   struct AIXAsmPrinter : public PowerPCAsmPrinter {
@@ -202,13 +202,13 @@ namespace {
       Data64bitsDirective = 0;       // we can't emit a 64-bit unit
       AlignmentIsInBytes = false;    // Alignment is by power of 2.
     }
-    
+
     virtual const char *getPassName() const {
       return "AIX PPC Assembly Printer";
     }
 
     void printConstantPool(MachineConstantPool *MCP);
-    bool runOnMachineFunction(MachineFunction &F);    
+    bool runOnMachineFunction(MachineFunction &F);
     bool doInitialization(Module &M);
     bool doFinalization(Module &M);
   };
@@ -258,7 +258,7 @@ namespace {
 
 /// SwitchStringSection - manage the changes required to output bytes as
 /// characters in a string vs. numeric decimal values
-/// 
+///
 static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
                                        StringSection &Current) {
   if (Current == None) {
@@ -269,7 +269,7 @@ static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
   } else if (Current == Alpha) {
     if (NewSect == None)
       O << "\"";
-    else if (NewSect == Numeric) 
+    else if (NewSect == Numeric)
       O << "\"\n"
         << "\t.byte ";
   } else if (Current == Numeric) {
@@ -310,8 +310,8 @@ static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
   O << '\n';
 }
 
-/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly 
-/// code for a MachineFunction to the given output stream, in a format that the 
+/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
+/// code for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
 FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
@@ -319,7 +319,7 @@ FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
 }
 
 /// createAIXAsmPrinterPass - Returns a pass that prints the PPC assembly code
-/// for a MachineFunction to the given output stream, in a format that the 
+/// for a MachineFunction to the given output stream, in a format that the
 /// AIX 5L assembler can deal with.
 ///
 FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
@@ -332,7 +332,7 @@ FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
 void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   int new_symbol;
-  
+
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
     if (Value *V = MO.getVRegValueOrNull()) {
@@ -355,7 +355,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
     std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
     abort();
     return;
-    
+
   case MachineOperand::MO_MachineBasicBlock: {
     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
@@ -391,7 +391,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
       O << "L" << Name << "$stub";
       return;
     }
-    
+
     // External or weakly linked global variables need non-lazily-resolved stubs
     if ((GV->isExternal() || GV->hasWeakLinkage() || GV->hasLinkOnceLinkage())){
       if (GV->hasLinkOnceLinkage())
@@ -405,7 +405,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
     O << Mang->getValueName(GV);
     return;
   }
-    
+
   default:
     O << "<unknown operand type: " << MO.getType() << ">";
     return;
@@ -431,17 +431,17 @@ void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
       SH = 32-SH;
     }
     if (FoundMnemonic) {
-      printOperand(MI, 0, MVT::i64); 
-      O << ", "; 
-      printOperand(MI, 1, MVT::i64); 
+      printOperand(MI, 0, MVT::i64);
+      O << ", ";
+      printOperand(MI, 1, MVT::i64);
       O << ", " << (unsigned int)SH << "\n";
       return;
     }
   }
-  
+
   if (printInstruction(MI))
     return; // Printer was automatically generated
-  
+
   assert(0 && "Unhandled instruction in asm writer!");
   abort();
   return;
@@ -490,7 +490,7 @@ bool DarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
   const std::vector<Constant*> &CP = MCP->getConstants();
   const TargetData &TD = TM.getTargetData();
- 
+
   if (CP.empty()) return;
 
   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
@@ -516,13 +516,13 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
       unsigned Align = TD.getTypeAlignmentShift(C->getType());
 
       if (C->isNullValue() && /* FIXME: Verify correct */
-          (I->hasInternalLinkage() || I->hasWeakLinkage() || 
+          (I->hasInternalLinkage() || I->hasWeakLinkage() ||
            I->hasLinkOnceLinkage())) {
         SwitchSection(O, CurSection, ".data");
         if (Size == 0) Size = 1;   // .comm Foo, 0 is undefined, avoid it.
         if (I->hasInternalLinkage())
           O << ".lcomm " << name << "," << Size << "," << Align;
-        else 
+        else
           O << ".comm " << name << "," << Size;
         O << "\t\t; ";
         WriteAsOperand(O, I, true, true, &M);
@@ -535,7 +535,7 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
             << ".private_extern " << name << '\n'
             << ".section __DATA,__datacoal_nt,coalesced,no_toc\n";
           LinkOnceStubs.insert(name);
-          break;  
+          break;
         case GlobalValue::WeakLinkage:   // FIXME: Verify correct for weak.
           // Nonnull linkonce -> weak
           O << "\t.weak " << name << "\n";
@@ -568,7 +568,7 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
     }
 
   // Output stubs for dynamically-linked functions
-  for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end(); 
+  for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
        i != e; ++i)
   {
     O << ".data\n";
@@ -597,22 +597,22 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
   // Output stubs for external global variables
   if (GVStubs.begin() != GVStubs.end())
     O << ".data\n.non_lazy_symbol_pointer\n";
-  for (std::set<std::string>::iterator i = GVStubs.begin(), e = GVStubs.end(); 
+  for (std::set<std::string>::iterator i = GVStubs.begin(), e = GVStubs.end();
        i != e; ++i) {
     O << "L" << *i << "$non_lazy_ptr:\n";
     O << "\t.indirect_symbol " << *i << "\n";
     O << "\t.long\t0\n";
   }
-  
+
   // Output stubs for link-once variables
   if (LinkOnceStubs.begin() != LinkOnceStubs.end())
     O << ".data\n.align 2\n";
-  for (std::set<std::string>::iterator i = LinkOnceStubs.begin(), 
+  for (std::set<std::string>::iterator i = LinkOnceStubs.begin(),
          e = LinkOnceStubs.end(); i != e; ++i) {
     O << "L" << *i << "$non_lazy_ptr:\n"
       << "\t.long\t" << *i << '\n';
   }
-  
+
   AsmPrinter::doFinalization(M);
   return false; // success
 }
@@ -672,7 +672,7 @@ bool AIXAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 void AIXAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
   const std::vector<Constant*> &CP = MCP->getConstants();
   const TargetData &TD = TM.getTargetData();
- 
+
   if (CP.empty()) return;
 
   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
@@ -689,7 +689,7 @@ bool AIXAsmPrinter::doInitialization(Module &M) {
   const TargetData &TD = TM.getTargetData();
   std::string CurSection;
 
-  O << "\t.machine \"ppc64\"\n" 
+  O << "\t.machine \"ppc64\"\n"
     << "\t.toc\n"
     << "\t.csect .text[PR]\n";
 
@@ -697,11 +697,11 @@ bool AIXAsmPrinter::doInitialization(Module &M) {
   for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) {
     if (!I->hasInitializer())
       continue;
- 
+
     std::string Name = I->getName();
     Constant *C = I->getInitializer();
     // N.B.: We are defaulting to writable strings
-    if (I->hasExternalLinkage()) { 
+    if (I->hasExternalLinkage()) {
       O << "\t.globl " << Name << '\n'
         << "\t.csect .data[RW],3\n";
     } else {
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 7dc59a299f..5eaf38f018 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -1,13 +1,13 @@
 //===-- PowerPCBranchSelector.cpp - Emit long conditional branches-*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by Nate Baegeman and is distributed under the
 // University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
-// This file contains a pass that scans a machine function to determine which 
+// This file contains a pass that scans a machine function to determine which
 // conditional branches need more than 16 bits of displacement to reach their
 // target basic block.  It does this in two passes; a calculation of basic block
 // positions pass, and a branch psuedo op to machine branch opcode pass.  This
@@ -30,32 +30,32 @@ namespace {
     // OffsetMap - Mapping between BB and byte offset from start of function
     std::map<MachineBasicBlock*, unsigned> OffsetMap;
 
-    /// bytesForOpcode - A convenience function for totalling up the number of 
+    /// bytesForOpcode - A convenience function for totalling up the number of
     /// bytes in a basic block.
     ///
     static unsigned bytesForOpcode(unsigned opcode) {
       switch (opcode) {
       case PPC::COND_BRANCH:
         // while this will be 4 most of the time, if we emit 12 it is just a
-        // minor pessimization that saves us from having to worry about 
+        // minor pessimization that saves us from having to worry about
         // keeping the offsets up to date later when we emit long branch glue.
         return 12;
       case PPC::IMPLICIT_DEF: // no asm emitted
         return 0;
         break;
-      default: 
+      default:
         return 4; // PowerPC instructions are all 4 bytes
         break;
       }
     }
-    
+
     virtual bool runOnMachineFunction(MachineFunction &Fn) {
       // Running total of instructions encountered since beginning of function
       unsigned ByteCount = 0;
 
       // For each MBB, add its offset to the offset map, and count up its
       // instructions
-      for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; 
+      for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
            ++MFI) {
         MachineBasicBlock *MBB = MFI;
         OffsetMap[MBB] = ByteCount;
@@ -80,10 +80,10 @@ namespace {
       // b .L_TARGET_MBB
       // b .L_FALLTHROUGH_MBB
 
-      for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; 
+      for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
            ++MFI) {
         MachineBasicBlock *MBB = MFI;
-        
+
         for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
              MBBI != EE; ++MBBI) {
           if (MBBI->getOpcode() == PPC::COND_BRANCH) {
@@ -92,11 +92,11 @@ namespace {
             // 1. bc opcode
             // 2. target MBB
             // 3. fallthrough MBB
-            MachineBasicBlock *trueMBB = 
+            MachineBasicBlock *trueMBB =
               MBBI->getOperand(2).getMachineBasicBlock();
-            MachineBasicBlock *falseMBB = 
+            MachineBasicBlock *falseMBB =
               MBBI->getOperand(3).getMachineBasicBlock();
-            
+
             int Displacement = OffsetMap[trueMBB] - ByteCount;
             unsigned Opcode = MBBI->getOperand(1).getImmedValue();
             unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 574e21e7cb..b957fe668a 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -1,12 +1,12 @@
 //===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
 // JIT-compile bytecode to native PowerPC.
 //
@@ -42,7 +42,7 @@ namespace {
     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
 
   public:
-    PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M) 
+    PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
       : TM(T), MCE(M) {}
 
     const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -58,7 +58,7 @@ namespace {
     /// emitWord - write a 32-bit word to memory at the current PC
     ///
     void emitWord(unsigned w) { MCE.emitWord(w); }
-    
+
     /// getValueBit - return the particular bit of Val
     ///
     unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
@@ -80,7 +80,7 @@ namespace {
 bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
                                                     MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC
-  PM.add(new PPC32CodeEmitter(*this, MCE)); 
+  PM.add(new PPC32CodeEmitter(*this, MCE));
   // Delete machine code for this function after emitting it
   PM.add(createMachineCodeDeleter());
   return false;
@@ -102,7 +102,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
                     << "\n");
     unsigned Instr = *Ref;
     intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
-    
+
     switch (Instr >> 26) {
     default: assert(0 && "Unknown branch user!");
     case 18:  // This is B or BL
@@ -142,36 +142,36 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
 
 static unsigned enumRegToMachineReg(unsigned enumReg) {
   switch (enumReg) {
-  case PPC::R0 :  case PPC::F0 :  case PPC::CR0:  return  0;  
-  case PPC::R1 :  case PPC::F1 :  case PPC::CR1:  return  1; 
+  case PPC::R0 :  case PPC::F0 :  case PPC::CR0:  return  0;
+  case PPC::R1 :  case PPC::F1 :  case PPC::CR1:  return  1;
   case PPC::R2 :  case PPC::F2 :  case PPC::CR2:  return  2;
-  case PPC::R3 :  case PPC::F3 :  case PPC::CR3:  return  3; 
-  case PPC::R4 :  case PPC::F4 :  case PPC::CR4:  return  4; 
+  case PPC::R3 :  case PPC::F3 :  case PPC::CR3:  return  3;
+  case PPC::R4 :  case PPC::F4 :  case PPC::CR4:  return  4;
   case PPC::R5 :  case PPC::F5 :  case PPC::CR5:  return  5;
-  case PPC::R6 :  case PPC::F6 :  case PPC::CR6:  return  6; 
-  case PPC::R7 :  case PPC::F7 :  case PPC::CR7:  return  7; 
+  case PPC::R6 :  case PPC::F6 :  case PPC::CR6:  return  6;
+  case PPC::R7 :  case PPC::F7 :  case PPC::CR7:  return  7;
   case PPC::R8 :  case PPC::F8 :  return  8;
-  case PPC::R9 :  case PPC::F9 :  return  9; 
-  case PPC::R10:  case PPC::F10:  return 10; 
+  case PPC::R9 :  case PPC::F9 :  return  9;
+  case PPC::R10:  case PPC::F10:  return 10;
   case PPC::R11:  case PPC::F11:  return 11;
-  case PPC::R12:  case PPC::F12:  return 12; 
-  case PPC::R13:  case PPC::F13:  return 13; 
+  case PPC::R12:  case PPC::F12:  return 12;
+  case PPC::R13:  case PPC::F13:  return 13;
   case PPC::R14:  case PPC::F14:  return 14;
-  case PPC::R15:  case PPC::F15:  return 15; 
-  case PPC::R16:  case PPC::F16:  return 16; 
+  case PPC::R15:  case PPC::F15:  return 15;
+  case PPC::R16:  case PPC::F16:  return 16;
   case PPC::R17:  case PPC::F17:  return 17;
-  case PPC::R18:  case PPC::F18:  return 18; 
-  case PPC::R19:  case PPC::F19:  return 19; 
+  case PPC::R18:  case PPC::F18:  return 18;
+  case PPC::R19:  case PPC::F19:  return 19;
   case PPC::R20:  case PPC::F20:  return 20;
   case PPC::R21:  case PPC::F21:  return 21;
-  case PPC::R22:  case PPC::F22:  return 22; 
-  case PPC::R23:  case PPC::F23:  return 23; 
+  case PPC::R22:  case PPC::F22:  return 22;
+  case PPC::R23:  case PPC::F23:  return 23;
   case PPC::R24:  case PPC::F24:  return 24;
-  case PPC::R25:  case PPC::F25:  return 25; 
-  case PPC::R26:  case PPC::F26:  return 26; 
+  case PPC::R25:  case PPC::F25:  return 25;
+  case PPC::R26:  case PPC::F26:  return 26;
   case PPC::R27:  case PPC::F27:  return 27;
-  case PPC::R28:  case PPC::F28:  return 28; 
-  case PPC::R29:  case PPC::F29:  return 29; 
+  case PPC::R28:  case PPC::F28:  return 28;
+  case PPC::R29:  case PPC::F29:  return 29;
   case PPC::R30:  case PPC::F30:  return 30;
   case PPC::R31:  case PPC::F31:  return 31;
   default:
@@ -181,7 +181,7 @@ static unsigned enumRegToMachineReg(unsigned enumReg) {
 }
 
 int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
-                                        
+
   int rv = 0; // Return value; defaults to 0 for unhandled cases
                   // or things that get fixed up later by the JIT.
   if (MO.isRegister()) {
diff --git a/lib/Target/PowerPC/PPCFrameInfo.h b/lib/Target/PowerPC/PPCFrameInfo.h
index a6f0e687ac..c1baf93041 100644
--- a/lib/Target/PowerPC/PPCFrameInfo.h
+++ b/lib/Target/PowerPC/PPCFrameInfo.h
@@ -1,10 +1,10 @@
 //===-- PowerPCFrameInfo.h - Define TargetFrameInfo for PowerPC -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 //
@@ -22,7 +22,7 @@ namespace llvm {
 class PowerPCFrameInfo: public TargetFrameInfo {
   const TargetMachine &TM;
   std::pair<unsigned, int> LR[1];
-  
+
 public:
   PowerPCFrameInfo(const TargetMachine &tm, bool LP64)
     : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 423eafe68f..84c05cb637 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -4,7 +4,7 @@
 //
 // This file was developed by Nate Begeman and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
@@ -47,7 +47,7 @@ namespace {
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
       addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
-      
+
       // PowerPC has no intrinsics for these particular operations
       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
       setOperationAction(ISD::MEMSET, MVT::Other, Expand);
@@ -56,14 +56,14 @@ namespace {
       // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-      
+
       // PowerPC has no SREM/UREM instructions
       setOperationAction(ISD::SREM, MVT::i32, Expand);
       setOperationAction(ISD::UREM, MVT::i32, Expand);
 
       setSetCCResultContents(ZeroOrOneSetCCResult);
       addLegalFPImmediate(+0.0); // Necessary for FSEL
-      addLegalFPImmediate(-0.0); // 
+      addLegalFPImmediate(-0.0); //
 
       computeRegisterProperties();
     }
@@ -72,16 +72,16 @@ namespace {
     /// lower the arguments for the specified function, into the specified DAG.
     virtual std::vector<SDOperand>
     LowerArguments(Function &F, SelectionDAG &DAG);
-    
+
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
                 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand, SDOperand>
     LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand,SDOperand>
     LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
@@ -102,8 +102,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineBasicBlock& BB = MF.front();
   std::vector<SDOperand> ArgValues;
-  
-  // Due to the rather complicated nature of the PowerPC ABI, rather than a 
+
+  // Due to the rather complicated nature of the PowerPC ABI, rather than a
   // fixed size array of physical args, for the sake of simplicity let the STL
   // handle tracking them for us.
   std::vector<unsigned> argVR, argPR, argOp;
@@ -111,7 +111,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   unsigned GPR_remaining = 8;
   unsigned FPR_remaining = 13;
   unsigned GPR_idx = 0, FPR_idx = 0;
-  static const unsigned GPR[] = { 
+  static const unsigned GPR[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
@@ -129,13 +129,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     bool needsLoad = false;
     bool ArgLive = !I->use_empty();
     MVT::ValueType ObjectVT = getValueType(I->getType());
-    
+
     switch (ObjectVT) {
     default: assert(0 && "Unhandled argument type!");
     case MVT::i1:
     case MVT::i8:
     case MVT::i16:
-    case MVT::i32: 
+    case MVT::i32:
       ObjSize = 4;
       if (!ArgLive) break;
       if (GPR_remaining > 0) {
@@ -170,7 +170,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
         newroot = argLo;
       } else {
-        needsLoad = true; 
+        needsLoad = true;
       }
       break;
       case MVT::f32:
@@ -179,7 +179,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       if (!ArgLive) break;
       if (FPR_remaining > 0) {
         MF.addLiveIn(FPR[FPR_idx]);
-        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT, 
+        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
                                             DAG.getRoot());
         --FPR_remaining;
         ++FPR_idx;
@@ -188,20 +188,20 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       }
       break;
     }
-    
+
     // We need to load the argument to a virtual register if we determined above
-    // that we ran out of physical registers of the appropriate type 
+    // that we ran out of physical registers of the appropriate type
     if (needsLoad) {
       unsigned SubregOffset = 0;
       if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
       if (ObjectVT == MVT::i16) SubregOffset = 2;
       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 
+      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
                         DAG.getConstant(SubregOffset, MVT::i32));
       argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
     }
-    
+
     // Every 4 bytes of argument space consumes one of the GPRs available for
     // argument passing.
     if (GPR_remaining > 0) {
@@ -212,7 +212,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     ArgOffset += ObjSize;
     if (newroot.Val)
       DAG.setRoot(newroot.getValue(1));
-    
+
     ArgValues.push_back(argt);
   }
 
@@ -228,7 +228,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
       MF.addLiveIn(GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
-      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 
+      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                     Val, FIN);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
@@ -292,8 +292,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
         NumBytes += 8;
         break;
       }
-    
-    // Just to be safe, we'll always reserve the full 24 bytes of linkage area 
+
+    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
     // plus 32 bytes of argument space in case any called code gets funky on us.
     if (NumBytes < 56) NumBytes = 56;
 
@@ -307,7 +307,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     // passing.
     SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
                                             DAG.getEntryNode());
-    
+
     // Figure out which arguments are going to go in registers, and which in
     // memory.  Also, if this is a vararg function, floating point operations
     // must be stored to our stack, and loaded into integer regs as well, if
@@ -315,7 +315,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     unsigned ArgOffset = 24;
     unsigned GPR_remaining = 8;
     unsigned FPR_remaining = 13;
-    
+
     std::vector<SDOperand> MemOps;
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
       // PtrOff will be used to store the current argument to the stack if a
@@ -323,7 +323,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
       MVT::ValueType ArgVT = getValueType(Args[i].second);
-      
+
       switch (ArgVT) {
       default: assert(0 && "Unexpected ValueType for argument!");
       case MVT::i1:
@@ -351,9 +351,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
         // in it, and store the other half to the stack.  If we have two or more
         // free GPRs, then we can pass both halves of the i64 in registers.
         if (GPR_remaining > 0) {
-          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 
+          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
             Args[i].first, DAG.getConstant(1, MVT::i32));
-          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 
+          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
             Args[i].first, DAG.getConstant(0, MVT::i32));
           args_to_use.push_back(Hi);
           --GPR_remaining;
@@ -420,14 +420,14 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     if (!MemOps.empty())
       Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
   }
-  
+
   std::vector<MVT::ValueType> RetVals;
   MVT::ValueType RetTyVT = getValueType(RetTy);
   if (RetTyVT != MVT::isVoid)
     RetVals.push_back(RetTyVT);
   RetVals.push_back(MVT::Other);
 
-  SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 
+  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
                                             Chain, Callee, args_to_use), 0);
   Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
   Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
@@ -462,7 +462,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   }
   return std::make_pair(Result, Chain);
 }
-               
+
 
 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
@@ -484,7 +484,7 @@ class ISel : public SelectionDAGISel {
   SelectionDAG *ISelDAG;  // Hack to support us having a dag->dag transform
                           // for sdiv and udiv until it is put into the future
                           // dag combiner.
-  
+
   /// ExprMap - As shared expressions are codegen'd, we keep track of which
   /// vreg the value is produced in, so we only emit one copy of each compiled
   /// tree.
@@ -496,15 +496,15 @@ class ISel : public SelectionDAGISel {
 public:
   ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
                             ISelDAG(0) {}
-  
+
   /// runOnFunction - Override this function in order to reset our per-function
   /// variables.
   virtual bool runOnFunction(Function &Fn) {
     // Make sure we re-emit a set of the global base reg if necessary
     GlobalBaseInitialized = false;
     return SelectionDAGISel::runOnFunction(Fn);
-  } 
-  
+  }
+
   /// InstructionSelectBasicBlock - This callback is invoked by
   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -512,7 +512,7 @@ public:
     // Codegen the basic block.
     ISelDAG = &DAG;
     Select(DAG.getRoot());
-    
+
     // Clear state used for selection.
     ExprMap.clear();
     ISelDAG = 0;
@@ -521,7 +521,7 @@ public:
   // dag -> dag expanders for integer divide by constant
   SDOperand BuildSDIVSequence(SDOperand N);
   SDOperand BuildUDIVSequence(SDOperand N);
-  
+
   unsigned getGlobalBaseReg();
   unsigned getConstDouble(double floatVal, unsigned Result);
   void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
@@ -532,7 +532,7 @@ public:
   unsigned SelectExpr(SDOperand N, bool Recording=false);
   unsigned SelectExprFP(SDOperand N, unsigned Result);
   void Select(SDOperand N);
-  
+
   bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
   void SelectBranchCC(SDOperand N);
 };
@@ -555,7 +555,7 @@ static unsigned ExactLog2(unsigned Val) {
 // not, since all 1's are not contiguous.
 static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
   bool isRun = true;
-  MB = 0; 
+  MB = 0;
   ME = 0;
 
   // look for first set bit
@@ -567,7 +567,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
       break;
     }
   }
-  
+
   // look for last set bit
   for (; i < 32; i++) {
     if ((Val & (1 << (31 - i))) == 0)
@@ -580,7 +580,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) != 0)
       break;
   }
-  
+
   // if we exhausted all the bits, we found a match at this point for 0*1*0*
   if (i == 32)
     return true;
@@ -596,7 +596,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) == 0)
       break;
   }
-  
+
   // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
   // the value is not a run of ones.
   if (i == 32)
@@ -620,7 +620,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
   if (N.getOpcode() != ISD::Constant) return 0;
 
   int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-  
+
   switch(Opcode) {
   default: return 0;
   case ISD::ADD:
@@ -666,7 +666,7 @@ static bool NodeHasRecordingVariant(unsigned NodeOpcode) {
   switch(NodeOpcode) {
   default: return false;
   case ISD::AND:
-  case ISD::OR: 
+  case ISD::OR:
     return true;
   }
 }
@@ -715,7 +715,7 @@ static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
 static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
   switch (Condition) {
   default: assert(0 && "Unknown condition!"); abort();
-  case ISD::SETULT: 
+  case ISD::SETULT:
   case ISD::SETLT:  Inv = false;  return 0;
   case ISD::SETUGE:
   case ISD::SETGE:  Inv = true;   return 0;
@@ -744,7 +744,7 @@ static unsigned IndexedOpForOp(unsigned Opcode) {
   return 0;
 }
 
-// Structure used to return the necessary information to codegen an SDIV as 
+// Structure used to return the necessary information to codegen an SDIV as
 // a multiply.
 struct ms {
   int m; // magic number
@@ -758,14 +758,14 @@ struct mu {
 };
 
 /// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1, 
+/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
 /// or -1.
 static struct ms magic(int d) {
   int p;
   unsigned int ad, anc, delta, q1, r1, q2, r2, t;
   const unsigned int two31 = 2147483648U; // 2^31
   struct ms mag;
-  
+
   ad = abs(d);
   t = two31 + ((unsigned int)d >> 31);
   anc = t - 1 - t%ad;   // absolute value of nc
@@ -847,7 +847,7 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
   int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
   ms magics = magic(d);
   // Multiply the numerator (operand 0) by the magic value
-  SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0), 
+  SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
                                  ISelDAG->getConstant(magics.m, MVT::i32));
   // If d > 0 and m < 0, add the numerator
   if (d > 0 && magics.m < 0)
@@ -857,10 +857,10 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
     Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
   // Shift right algebraic if shift value is nonzero
   if (magics.s > 0)
-    Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q, 
+    Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
                          ISelDAG->getConstant(magics.s, MVT::i32));
   // Extract the sign bit and add it to the quotient
-  SDOperand T = 
+  SDOperand T =
     ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
   return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
 }
@@ -870,21 +870,21 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
-  unsigned d = 
+  unsigned d =
     (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
   mu magics = magicu(d);
   // Multiply the numerator (operand 0) by the magic value
-  SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0), 
+  SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
                                  ISelDAG->getConstant(magics.m, MVT::i32));
   if (magics.a == 0) {
-    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q, 
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
                          ISelDAG->getConstant(magics.s, MVT::i32));
   } else {
     SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
-    NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ, 
+    NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
                            ISelDAG->getConstant(1, MVT::i32));
     NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
-    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ, 
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
                            ISelDAG->getConstant(magics.s-1, MVT::i32));
   }
   return Q;
@@ -906,7 +906,7 @@ unsigned ISel::getGlobalBaseReg() {
   return GlobalBaseReg;
 }
 
-/// getConstDouble - Loads a floating point value into a register, via the 
+/// getConstDouble - Loads a floating point value into a register, via the
 /// Constant Pool.  Optionally takes a register in which to load the value.
 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
   unsigned Tmp1 = MakeReg(MVT::i32);
@@ -920,7 +920,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
   return Result;
 }
 
-/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result.  If 
+/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result.  If
 /// Inv is true, then invert the result.
 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   unsigned IntCR = MakeReg(MVT::i32);
@@ -937,7 +937,7 @@ void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   }
 }
 
-/// SelectBitfieldInsert - turn an or of two masked values into 
+/// SelectBitfieldInsert - turn an or of two masked values into
 /// the rotate left word immediate then mask insert (rlwimi) instruction.
 /// Returns true on success, false if the caller still needs to select OR.
 ///
@@ -951,15 +951,15 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
   unsigned Op0Opc = OR.getOperand(0).getOpcode();
   unsigned Op1Opc = OR.getOperand(1).getOpcode();
-  
+
   // Verify that we have the correct opcodes
   if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
     return false;
   if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
     return false;
-    
+
   // Generate Mask value for Target
-  if (ConstantSDNode *CN = 
+  if (ConstantSDNode *CN =
       dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
     switch(Op0Opc) {
     case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
@@ -969,30 +969,30 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   } else {
     return false;
   }
-  
+
   // Generate Mask value for Insert
-  if (ConstantSDNode *CN = 
+  if (ConstantSDNode *CN =
       dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
     switch(Op1Opc) {
-    case ISD::SHL: 
-      Amount = CN->getValue(); 
+    case ISD::SHL:
+      Amount = CN->getValue();
       InsMask <<= Amount;
       if (Op0Opc == ISD::SRL) IsRotate = true;
       break;
-    case ISD::SRL: 
-      Amount = CN->getValue(); 
-      InsMask >>= Amount; 
+    case ISD::SRL:
+      Amount = CN->getValue();
+      InsMask >>= Amount;
       Amount = 32-Amount;
       if (Op0Opc == ISD::SHL) IsRotate = true;
       break;
-    case ISD::AND: 
+    case ISD::AND:
       InsMask &= (unsigned)CN->getValue();
       break;
     }
   } else {
     return false;
   }
-  
+
   // Verify that the Target mask and Insert mask together form a full word mask
   // and that the Insert mask is a run of set bits (which implies both are runs
   // of set bits).  Given that, Select the arguments and generate the rlwimi
@@ -1002,7 +1002,7 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
     unsigned Tmp1, Tmp2;
     // Check for rotlwi / rotrwi here, a special case of bitfield insert
     // where both bitfield halves are sourced from the same value.
-    if (IsRotate && 
+    if (IsRotate &&
         OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
       Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
       BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
@@ -1039,12 +1039,12 @@ unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
 unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
   unsigned Result, Tmp1, Tmp2;
   bool AlreadySelected = false;
-  static const unsigned CompareOpcodes[] = 
+  static const unsigned CompareOpcodes[] =
     { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-  
+
   // Allocate a condition register for this expression
   Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
-  
+
   // If the first operand to the select is a SETCC node, then we can fold it
   // into the branch that selects which value to return.
   if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
@@ -1054,12 +1054,12 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
 
     // Pass the optional argument U to getImmediateForOpcode for SETCC,
     // so that it knows whether the SETCC immediate range is signed or not.
-    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC, 
+    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
                                    Tmp2, U)) {
-      // For comparisons against zero, we can implicity set CR0 if a recording 
+      // For comparisons against zero, we can implicity set CR0 if a recording
       // variant (e.g. 'or.' instead of 'or') of the instruction that defines
       // operand zero of the SetCC node is available.
-      if (0 == Tmp2 && 
+      if (0 == Tmp2 &&
           NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode()) &&
           SetCC->getOperand(0).Val->hasOneUse()) {
         RecordSuccess = false;
@@ -1098,7 +1098,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
   return Result;
 }
 
-unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, 
+unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
                             unsigned &Idx) {
   bool Inv0, Inv1;
   unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
@@ -1148,7 +1148,7 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
       offset = imm;
       return false;
-    } 
+    }
     offset = SelectExpr(N.getOperand(1));
     return true;
   }
@@ -1159,14 +1159,14 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
 
 void ISel::SelectBranchCC(SDOperand N)
 {
-  MachineBasicBlock *Dest = 
+  MachineBasicBlock *Dest =
     cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
 
   bool Inv;
   unsigned Opc, CCReg, Idx;
   Select(N.getOperand(0));  //chain
   CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
-  
+
   // Iterate to the next basic block, unless we're already at the end of the
   ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
   if (++It == E) It = BB;
@@ -1176,7 +1176,7 @@ void ISel::SelectBranchCC(SDOperand N)
   // if necessary by the branch selection pass.  Otherwise, emit a standard
   // conditional branch.
   if (N.getOpcode() == ISD::BRCONDTWOWAY) {
-    MachineBasicBlock *Fallthrough = 
+    MachineBasicBlock *Fallthrough =
       cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
     if (Dest != It) {
       BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
@@ -1221,7 +1221,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       MVT::ValueType VT = SetCC->getOperand(0).getValueType();
       unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
       unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-      
+
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
       if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
         switch(SetCC->getCondition()) {
@@ -1282,13 +1282,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       assert(0 && "Should never get here");
       return 0;
     }
-    
+
     bool Inv;
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
 
-    // Create an iterator with which to insert the MBB for copying the false 
+    // Create an iterator with which to insert the MBB for copying the false
     // value and the MBB to hold the PHI instruction for this SetCC.
     MachineBasicBlock *thisMBB = BB;
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1328,7 +1328,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
   }
 
   case ISD::FNEG:
-    if (!NoExcessFPPrecision && 
+    if (!NoExcessFPPrecision &&
         ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -1339,7 +1339,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
       Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-    } else if (!NoExcessFPPrecision && 
+    } else if (!NoExcessFPPrecision &&
         ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
@@ -1358,23 +1358,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::FABS:
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_ROUND:
-    assert (DestType == MVT::f32 && 
-            N.getOperand(0).getValueType() == MVT::f64 && 
+    assert (DestType == MVT::f32 &&
+            N.getOperand(0).getValueType() == MVT::f64 &&
             "only f64 to f32 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_EXTEND:
-    assert (DestType == MVT::f64 && 
-            N.getOperand(0).getValueType() == MVT::f32 && 
+    assert (DestType == MVT::f64 &&
+            N.getOperand(0).getValueType() == MVT::f32 &&
             "only f32 to f64 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
@@ -1386,13 +1386,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
     Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
     return Result;
-    
+
   case ISD::ConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     Result = getConstDouble(CN->getValue(), Result);
     return Result;
   }
-    
+
   case ISD::ADD:
     if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
         N.getOperand(0).Val->hasOneUse()) {
@@ -1460,16 +1460,16 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
 
   case ISD::UINT_TO_FP:
   case ISD::SINT_TO_FP: {
-    assert (N.getOperand(0).getValueType() == MVT::i32 
+    assert (N.getOperand(0).getValueType() == MVT::i32
             && "int to float must operate on i32");
     bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
     Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
     Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
     Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
-    
+
     int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
     MachineConstantPool *CP = BB->getParent()->getConstantPool();
-    
+
     if (IsUnsigned) {
       unsigned ConstF = getConstDouble(0x1.000000p52);
       // Store the hi & low halves of the fp value, currently in int regs
@@ -1542,9 +1542,9 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
   if (ISD::CopyFromReg == opcode)
     DestType = N.getValue(0).getValueType();
-    
+
   if (DestType == MVT::f64 || DestType == MVT::f32)
-    if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && 
+    if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
         ISD::UNDEF != opcode && ISD::CALL != opcode)
       return SelectExprFP(N, Result);
 
@@ -1591,7 +1591,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
     addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
     return Result;
-  
+
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     Tmp1 = MakeReg(MVT::i32);
@@ -1612,7 +1612,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
       Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
     bool sext = (ISD::SEXTLOAD == opcode);
-    
+
     // Make sure we generate both values.
     if (Result != 1)
       ExprMap[N.getValue(1)] = 1;   // Generate the token
@@ -1632,7 +1632,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     case MVT::f32: Opc = PPC::LFS; break;
     case MVT::f64: Opc = PPC::LFD; break;
     }
-    
+
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
       Tmp1 = MakeReg(MVT::i32);
       int CPI = CP->getIndex();
@@ -1655,10 +1655,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     return Result;
   }
-    
+
   case ISD::CALL: {
     unsigned GPR_idx = 0, FPR_idx = 0;
-    static const unsigned GPR[] = { 
+    static const unsigned GPR[] = {
       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
@@ -1673,13 +1673,13 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
     MachineInstr *CallMI;
     // Emit the correct call instruction based on the type of symbol called.
-    if (GlobalAddressSDNode *GASD = 
+    if (GlobalAddressSDNode *GASD =
         dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
                                                            true);
-    } else if (ExternalSymbolSDNode *ESSDN = 
+    } else if (ExternalSymbolSDNode *ESSDN =
                dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
                                                             true);
     } else {
       Tmp1 = SelectExpr(N.getOperand(1));
@@ -1688,7 +1688,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
         .addReg(PPC::R12);
     }
-       
+
     // Load the register args to virtual regs
     std::vector<unsigned> ArgVR;
     for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
@@ -1718,7 +1718,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
         break;
       }
     }
-    
+
     // Put the call instruction in the correct place in the MachineBasicBlock
     BB->push_back(CallMI);
 
@@ -1750,17 +1750,17 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i16:
-      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
       break;
     case MVT::i8:
-      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
       break;
     case MVT::i1:
       BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
       break;
     }
     return Result;
-    
+
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
@@ -1779,7 +1779,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1791,7 +1791,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRA:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1802,7 +1802,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-  
+
   case ISD::ADD:
     assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
     Tmp1 = SelectExpr(N.getOperand(0));
@@ -1823,7 +1823,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
   case ISD::AND:
     if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC || 
+      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
           N.getOperand(1).getOpcode() == ISD::SETCC) {
         bool Inv;
         Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
@@ -1858,12 +1858,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     RecordSuccess = true;
     return Result;
-  
+
   case ISD::OR:
     if (SelectBitfieldInsert(N, Result))
       return Result;
     if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC || 
+      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
           N.getOperand(1).getOpcode() == ISD::SETCC) {
         bool Inv;
         Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
@@ -1951,7 +1951,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::MUL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
@@ -1992,7 +1992,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     // constants to implement it as a multiply instead.
     case 4:
       ExprMap.erase(N);
-      if (opcode == ISD::SDIV) 
+      if (opcode == ISD::SDIV)
         return SelectExpr(BuildSDIVSequence(N));
       else
         return SelectExpr(BuildUDIVSequence(N));
@@ -2080,7 +2080,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     return Result+N.ResNo;
   }
-    
+
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT: {
     bool U = (ISD::FP_TO_UINT == opcode);
@@ -2151,10 +2151,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     assert(0 && "Should never get here");
     return 0;
   }
- 
+
   case ISD::SETCC:
     if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-      if (ConstantSDNode *CN = 
+      if (ConstantSDNode *CN =
           dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
         // We can codegen setcc op, imm very efficiently compared to a brcond.
         // Check for those cases here.
@@ -2226,7 +2226,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
           return Result;
         }
       }
-    
+
       bool Inv;
       unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
       MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
@@ -2234,14 +2234,14 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     assert(0 && "Is this legal?");
     return 0;
-    
+
   case ISD::SELECT: {
     bool Inv;
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
 
-    // Create an iterator with which to insert the MBB for copying the false 
+    // Create an iterator with which to insert the MBB for copying the false
     // value and the MBB to hold the PHI instruction for this SetCC.
     MachineBasicBlock *thisMBB = BB;
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -2313,7 +2313,7 @@ void ISel::Select(SDOperand N) {
     return;  // Already selected.
 
   SDNode *Node = N.Val;
-  
+
   switch (Node->getOpcode()) {
   default:
     Node->dump(); std::cerr << "\n";
@@ -2338,7 +2338,7 @@ void ISel::Select(SDOperand N) {
     BuildMI(BB, PPC::B, 1).addMBB(Dest);
     return;
   }
-  case ISD::BRCOND: 
+  case ISD::BRCOND:
   case ISD::BRCONDTWOWAY:
     SelectBranchCC(N);
     return;
@@ -2346,9 +2346,9 @@ void ISel::Select(SDOperand N) {
     Select(N.getOperand(0));
     Tmp1 = SelectExpr(N.getOperand(1));
     Tmp2 = cast<RegSDNode>(N)->getReg();
-    
+
     if (Tmp1 != Tmp2) {
-      if (N.getOperand(1).getValueType() == MVT::f64 || 
+      if (N.getOperand(1).getValueType() == MVT::f64 ||
           N.getOperand(1).getValueType() == MVT::f32)
         BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
       else
@@ -2393,8 +2393,8 @@ void ISel::Select(SDOperand N) {
     }
     BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
     return;
-  case ISD::TRUNCSTORE: 
-  case ISD::STORE: 
+  case ISD::TRUNCSTORE:
+  case ISD::STORE:
     {
       SDOperand Chain   = N.getOperand(0);
       SDOperand Value   = N.getOperand(1);
@@ -2428,7 +2428,7 @@ void ISel::Select(SDOperand N) {
       {
         int offset;
         bool idx = SelectAddr(Address, Tmp2, offset);
-        if (idx) { 
+        if (idx) {
           Opc = IndexedOpForOp(Opc);
           BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
         } else {
@@ -2457,6 +2457,6 @@ void ISel::Select(SDOperand N) {
 /// description file.
 ///
 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
-  return new ISel(TM);  
+  return new ISel(TM);
 }
 
diff --git a/lib/Target/PowerPC/PPCInstrBuilder.h b/lib/Target/PowerPC/PPCInstrBuilder.h
index d400acf0df..ab774e2553 100644
--- a/lib/Target/PowerPC/PPCInstrBuilder.h
+++ b/lib/Target/PowerPC/PPCInstrBuilder.h
@@ -1,10 +1,10 @@
 //===-- PowerPCInstrBuilder.h - Aides for building PPC insts ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file exposes functions that may be used with BuildMI from the
@@ -30,7 +30,7 @@ namespace llvm {
 /// This allows a constant offset to be specified as well...
 ///
 inline const MachineInstrBuilder&
-addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, 
+addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
                   bool mem = true) {
   if (mem)
     return MIB.addSImm(Offset).addFrameIndex(FI);
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index d8f008a1fe..50ad423cf7 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1,10 +1,10 @@
 //===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetInstrInfo class.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index 17ef80328d..35bab982f0 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -1,10 +1,10 @@
 //===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetInstrInfo class.
@@ -47,7 +47,7 @@ public:
     case PPC::BGE: return PPC::BLT;
     case PPC::BGT: return PPC::BLE;
     case PPC::BLE: return PPC::BGT;
-    } 
+    }
   }
 };
 
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index 7c150bfb2d..416b425401 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -1,10 +1,10 @@
 //===-- PPC32JITInfo.cpp - Implement the JIT interfaces for the PowerPC ---===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the JIT interfaces for the 32-bit PowerPC target.
@@ -66,9 +66,9 @@ asm(
     "stw r11, 280(r1)\n"    // Set up a proper stack frame
     "stmw r3, 156(r1)\n"    // Save all of the integer registers
     // Save all call-clobbered FP regs.
-    "stfd f1, 44(r1)\n"  "stfd f2, 52(r1)\n"  "stfd f3, 60(r1)\n" 
-    "stfd f4, 68(r1)\n" "stfd f5, 76(r1)\n" "stfd f6, 84(r1)\n" 
-    "stfd f7, 92(r1)\n" "stfd f8, 100(r1)\n" "stfd f9, 108(r1)\n" 
+    "stfd f1, 44(r1)\n"  "stfd f2, 52(r1)\n"  "stfd f3, 60(r1)\n"
+    "stfd f4, 68(r1)\n" "stfd f5, 76(r1)\n" "stfd f6, 84(r1)\n"
+    "stfd f7, 92(r1)\n" "stfd f8, 100(r1)\n" "stfd f9, 108(r1)\n"
     "stfd f10, 116(r1)\n" "stfd f11, 124(r1)\n" "stfd f12, 132(r1)\n"
     "stfd f13, 140(r1)\n"
 
@@ -112,7 +112,7 @@ extern "C" void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) {
       CameFromOrig[-1] = CameFromOrigInst;
     }
   }
-  
+
   // Locate the start of the stub.  If this is a short call, adjust backwards
   // the short amount, otherwise the full amount.
   bool isShortStub = (*CameFromStub >> 26) == 18;
@@ -135,9 +135,9 @@ extern "C" void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) {
   register unsigned *IRR asm ("r2") = IntRegs;
   register double   *FRR asm ("r3") = FPRegs;
   __asm__ __volatile__ (
-  "lfd f1, 0(%0)\n"  "lfd f2, 8(%0)\n"  "lfd f3, 16(%0)\n" 
-  "lfd f4, 24(%0)\n" "lfd f5, 32(%0)\n" "lfd f6, 40(%0)\n" 
-  "lfd f7, 48(%0)\n" "lfd f8, 56(%0)\n" "lfd f9, 64(%0)\n" 
+  "lfd f1, 0(%0)\n"  "lfd f2, 8(%0)\n"  "lfd f3, 16(%0)\n"
+  "lfd f4, 24(%0)\n" "lfd f5, 32(%0)\n" "lfd f6, 40(%0)\n"
+  "lfd f7, 48(%0)\n" "lfd f8, 56(%0)\n" "lfd f9, 64(%0)\n"
   "lfd f10, 72(%0)\n" "lfd f11, 80(%0)\n" "lfd f12, 88(%0)\n"
   "lfd f13, 96(%0)\n"
   "lmw r3, 0(%1)\n"  // Load all integer regs
@@ -147,13 +147,13 @@ extern "C" void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) {
   "mtctr r0\n"       // Put it into the CTR register
   "lwz r1,0(r1)\n"   // Pop two frames off
   "bctr\n" ::        // Return to stub!
-  "b" (FRR), "b" (IRR)); 
+  "b" (FRR), "b" (IRR));
 #endif
 }
 
 
 
-TargetJITInfo::LazyResolverFn 
+TargetJITInfo::LazyResolverFn
 PPC32JITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
   JITCompilerFunction = Fn;
   return PPC32CompilationCallback;
diff --git a/lib/Target/PowerPC/PPCJITInfo.h b/lib/Target/PowerPC/PPCJITInfo.h
index ce4d1d36ff..09659521c7 100644
--- a/lib/Target/PowerPC/PPCJITInfo.h
+++ b/lib/Target/PowerPC/PPCJITInfo.h
@@ -1,10 +1,10 @@
 //===- PowerPCJITInfo.h - PowerPC impl. of the JIT interface ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetJITInfo class.
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 6a238fd85c..66bbea7534 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1,10 +1,10 @@
 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
@@ -38,7 +38,7 @@ namespace llvm {
 
 PPC32RegisterInfo::PPC32RegisterInfo()
   : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
-  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;    
+  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
@@ -79,12 +79,12 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
   abort();
 }
 
-void 
+void
 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  static const unsigned Opcode[] = { 
-    PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD 
+  static const unsigned Opcode[] = {
+    PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
   };
   unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
@@ -102,8 +102,8 @@ void
 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx) const{
-  static const unsigned Opcode[] = { 
-    PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD 
+  static const unsigned Opcode[] = {
+    PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
   };
   unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
@@ -163,7 +163,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       // alignment boundary.
       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
       Amount = (Amount+Align-1)/Align*Align;
-      
+
       // Replace the pseudo instruction with a new instruction...
       if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
         MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
@@ -184,7 +184,7 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
-  
+
   while (!MI.getOperand(i).isFrameIndex()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -206,7 +206,7 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   // SP before having the stack size subtracted from it, then add the stack size
   // to Offset to get the correct offset.
   Offset += MF.getFrameInfo()->getStackSize();
-  
+
   if (Offset > 32767 || Offset < -32768) {
     // Insert a set of r0 with the full offset value before the ld, st, or add
     MachineBasicBlock *MBB = MI.getParent();
@@ -232,15 +232,15 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineInstr *MI;
-  
+
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI->getStackSize();
 
   // If we have calls, we cannot use the red zone to store callee save registers
   // and we must set up a stack frame, so calculate the necessary size here.
   if (MFI->hasCalls()) {
-    // We reserve argument space for call sites in the function immediately on 
-    // entry to the current function.  This eliminates the need for add/sub 
+    // We reserve argument space for call sites in the function immediately on
+    // entry to the current function.  This eliminates the need for add/sub
     // brackets around call sites.
     NumBytes += MFI->getMaxCallFrameSize();
   }
@@ -248,7 +248,7 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
   // Do we need to allocate space on the stack?
   if (NumBytes == 0) return;
 
-  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom 
+  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom
   // of the stack and round the size to a multiple of the alignment.
   unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
   unsigned GPRSize = getSpillSize(PPC::R1)/8;
@@ -272,7 +272,7 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
     MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
     MBB.insert(MBBI, MI);
   }
-  
+
   if (hasFP(MF)) {
     MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
     MBB.insert(MBBI, MI);
@@ -288,7 +288,7 @@ void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
   MachineInstr *MI;
   assert(MBBI->getOpcode() == PPC::BLR &&
          "Can only insert epilog into returning blocks");
-  
+
   // Get the number of bytes allocated from the FrameInfo...
   unsigned NumBytes = MFI->getStackSize();
   unsigned GPRSize = getSpillSize(PPC::R31)/8;
@@ -319,7 +319,7 @@ PPC32RegisterInfo::getRegClassForType(const Type* Ty) const {
     case Type::IntTyID:
     case Type::UIntTyID:
     case Type::PointerTyID: return &GPRCInstance;
-     
+
     case Type::FloatTyID:
     case Type::DoubleTyID: return &FPRCInstance;
   }
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index e3750481d7..cc70114a39 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -1,10 +1,10 @@
 //===- PPC32RegisterInfo.h - PowerPC32 Register Information Impl -*- C++ -*-==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the MRegisterInfo class.
@@ -36,7 +36,7 @@ public:
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIndex) const;
-  
+
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
diff --git a/lib/Target/PowerPC/PPCRelocations.h b/lib/Target/PowerPC/PPCRelocations.h
index a3eb760043..474d733664 100644
--- a/lib/Target/PowerPC/PPCRelocations.h
+++ b/lib/Target/PowerPC/PPCRelocations.h
@@ -1,10 +1,10 @@
 //===- PPC32Relocations.h - PPC32 Code Relocations --------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the PowerPC 32-bit target-specific relocation types.
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 6286735603..b4f6fa497f 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -1,12 +1,12 @@
 //===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 //
 //===----------------------------------------------------------------------===//
 
@@ -31,13 +31,13 @@ using namespace llvm;
 
 namespace llvm {
   bool PPCCRopts;
-  cl::opt<bool> AIX("aix", 
-                    cl::desc("Generate AIX/xcoff instead of Darwin/MachO"), 
+  cl::opt<bool> AIX("aix",
+                    cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
                     cl::Hidden);
-  cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", 
-                             cl::desc("Enable LSR for PPC (beta)"), 
+  cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
+                             cl::desc("Enable LSR for PPC (beta)"),
                              cl::Hidden);
-  cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts", 
+  cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
                             cl::desc("Enable opts using condition regs (beta)"),
                             cl::location(PPCCRopts),
                             cl::init(false),
@@ -47,13 +47,13 @@ namespace llvm {
 namespace {
   const std::string PPC32ID = "PowerPC/32bit";
   const std::string PPC64ID = "PowerPC/64bit";
-  
+
   // Register the targets
-  RegisterTarget<PPC32TargetMachine> 
+  RegisterTarget<PPC32TargetMachine>
   X("ppc32", "  PowerPC 32-bit");
 
 #if 0
-  RegisterTarget<PPC64TargetMachine> 
+  RegisterTarget<PPC64TargetMachine>
   Y("ppc64", "  PowerPC 64-bit (unimplemented)");
 #endif
 }
@@ -84,7 +84,7 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
     PM.add(createLoopStrengthReducePass());
     PM.add(createCFGSimplificationPass());
   }
-  
+
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
 
@@ -116,15 +116,15 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
     PM.add(createMachineFunctionPrinterPass(&std::cerr));
 
   PM.add(createPrologEpilogCodeInserter());
-  
+
   // Must run branch selection immediately preceding the asm printer
   PM.add(createPPCBranchSelectionPass());
-  
+
   if (AIX)
     PM.add(createAIXAsmPrinter(Out, *this));
   else
     PM.add(createDarwinAsmPrinter(Out, *this));
-    
+
   PM.add(createMachineCodeDeleter());
   return false;
 }
@@ -172,7 +172,7 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
 /// PowerPCTargetMachine ctor - Create an ILP32 architecture model
 ///
 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
-  : PowerPCTargetMachine(PPC32ID, IL, 
+  : PowerPCTargetMachine(PPC32ID, IL,
                          TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
 
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index 278d31a267..9b167138bc 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -1,12 +1,12 @@
 //===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the PowerPC specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/PowerPC/PowerPCInstrInfo.h b/lib/Target/PowerPC/PowerPCInstrInfo.h
index e0651ba8f4..e1ab251191 100644
--- a/lib/Target/PowerPC/PowerPCInstrInfo.h
+++ b/lib/Target/PowerPC/PowerPCInstrInfo.h
@@ -1,10 +1,10 @@
 //===- PowerPCInstrInfo.h - PowerPC Instruction Information -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetInstrInfo class.
@@ -23,7 +23,7 @@ namespace llvm {
       VMX   = 1 << 0,
       PPC64 = 1 << 1,
     };
-  
+
     enum {
       None = 0,
       Gpr = 1,
diff --git a/lib/Target/PowerPC/PowerPCTargetMachine.h b/lib/Target/PowerPC/PowerPCTargetMachine.h
index f4e568bfef..34699c82f8 100644
--- a/lib/Target/PowerPC/PowerPCTargetMachine.h
+++ b/lib/Target/PowerPC/PowerPCTargetMachine.h
@@ -1,12 +1,12 @@
 //===-- PowerPCTargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the PowerPC-specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//