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author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-12 05:02:51 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-12 05:02:51 +0000 |
commit | f9318673178309288f9320efe02d529419ac32a2 (patch) | |
tree | 013788dd2f9e5f08fb273078ad96a53168c4185e /lib/Target/R600/AMDGPUAsmPrinter.cpp | |
parent | c429b5cca1a2710657b746b774e606f10200d89e (diff) | |
download | llvm-f9318673178309288f9320efe02d529419ac32a2.tar.gz llvm-f9318673178309288f9320efe02d529419ac32a2.tar.bz2 llvm-f9318673178309288f9320efe02d529419ac32a2.tar.xz |
R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
Patch by: Jay Cornwall
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUAsmPrinter.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPUAsmPrinter.cpp | 44 |
1 files changed, 36 insertions, 8 deletions
diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp index e039b773de..f3ccce72c5 100644 --- a/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -45,32 +45,60 @@ extern "C" void LLVMInitializeR600AsmPrinter() { TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass); } +AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) +{ + DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() && + ! Streamer.hasRawTextSupport(); +} + /// We need to override this function so we can avoid /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle. bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { - const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); - if (STM.dumpCode()) { -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - MF.dump(); -#endif - } SetupMachineFunction(MF); if (OutStreamer.hasRawTextSupport()) { OutStreamer.EmitRawText("@" + MF.getName() + ":"); } - const MCSectionELF *ConfigSection = getObjFileLowering().getContext() - .getELFSection(".AMDGPU.config", + MCContext &Context = getObjFileLowering().getContext(); + const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0, SectionKind::getReadOnly()); OutStreamer.SwitchSection(ConfigSection); + const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { EmitProgramInfoSI(MF); } else { EmitProgramInfoR600(MF); } + + DisasmLines.clear(); + HexLines.clear(); + DisasmLineMaxLen = 0; + OutStreamer.SwitchSection(getObjFileLowering().getTextSection()); EmitFunctionBody(); + + if (STM.dumpCode()) { +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + MF.dump(); +#endif + + if (DisasmEnabled) { + OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm", + ELF::SHT_NOTE, 0, + SectionKind::getReadOnly())); + + for (size_t i = 0; i < DisasmLines.size(); ++i) { + std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' '); + Comment += " ; " + HexLines[i] + "\n"; + + OutStreamer.EmitBytes(StringRef(DisasmLines[i])); + OutStreamer.EmitBytes(StringRef(Comment)); + } + } + } + return false; } |