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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
| commit | 38d5e1c36d954f1ff6489f58efd1d4865217cf9b (patch) | |
| tree | 451454dd8bf6ea5ec2f3ea021da2c7f6de4a928a /lib/Target/R600/AMDGPURegisterInfo.h | |
| parent | 636298ba64fd07d4ddcae6005e7fc1db43eb5335 (diff) | |
| download | llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.gz llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.bz2 llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.xz | |
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPURegisterInfo.h')
| -rw-r--r-- | lib/Target/R600/AMDGPURegisterInfo.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPURegisterInfo.h b/lib/Target/R600/AMDGPURegisterInfo.h index 7cbd34b8a7..135d3dd020 100644 --- a/lib/Target/R600/AMDGPURegisterInfo.h +++ b/lib/Target/R600/AMDGPURegisterInfo.h @@ -50,6 +50,10 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { assert(!"Unimplemented"); return NULL; } + /// \returns the sub reg enum value for the given \p Channel + /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) + unsigned getSubRegFromChannel(unsigned Channel) const; + const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const; void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, |