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| author | Vincent Lejeune <vljn@ovi.com> | 2013-10-01 19:32:38 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-10-01 19:32:38 +0000 |
| commit | 5b00e833fabbf5bdf2973c63c39d4a0d0143853a (patch) | |
| tree | 396f9581ca7af7e70bbd9d371bb7cfa628388ce4 /lib/Target/R600/AMDILInstrInfo.td | |
| parent | db3de106376558c7425d557b1b980f631107cd14 (diff) | |
| download | llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.tar.gz llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.tar.bz2 llvm-5b00e833fabbf5bdf2973c63c39d4a0d0143853a.tar.xz | |
R600: Enable -verify-machineinstrs in some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDILInstrInfo.td')
| -rw-r--r-- | lib/Target/R600/AMDILInstrInfo.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/R600/AMDILInstrInfo.td b/lib/Target/R600/AMDILInstrInfo.td index f7d0bd5734..0f0c88db93 100644 --- a/lib/Target/R600/AMDILInstrInfo.td +++ b/lib/Target/R600/AMDILInstrInfo.td @@ -118,15 +118,15 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern> // Multiclass Instruction formats //===--------------------------------------------------------------------===// // Multiclass that handles branch instructions -multiclass BranchConditional<SDNode Op> { +multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { def _i32 : ILFormat<(outs), - (ins brtarget:$target, GPRI32:$src0), + (ins brtarget:$target, rci:$src0), "; i32 Pseudo branch instruction", - [(Op bb:$target, GPRI32:$src0)]>; + [(Op bb:$target, (i32 rci:$src0))]>; def _f32 : ILFormat<(outs), - (ins brtarget:$target, GPRF32:$src0), + (ins brtarget:$target, rcf:$src0), "; f32 Pseudo branch instruction", - [(Op bb:$target, GPRF32:$src0)]>; + [(Op bb:$target, (f32 rcf:$src0))]>; } // Only scalar types should generate flow control |