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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 19:39:40 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 19:39:40 +0000 |
| commit | fc207d8f57d3bd27aa0dc2dd40ecd344229477d3 (patch) | |
| tree | 9a3ee76bd693447f55a9b5efa69c85adab1253af /lib/Target/R600/MCTargetDesc | |
| parent | 75ddd4cd4c726b3bf93b2a83b51d95a505ce0739 (diff) | |
| download | llvm-fc207d8f57d3bd27aa0dc2dd40ecd344229477d3.tar.gz llvm-fc207d8f57d3bd27aa0dc2dd40ecd344229477d3.tar.bz2 llvm-fc207d8f57d3bd27aa0dc2dd40ecd344229477d3.tar.xz | |
R600/SI: simplify and fix SMRD encoding
The _SGPR variants where wrong.
Patch by: Christian König
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174653 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/MCTargetDesc')
| -rw-r--r-- | lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h | 4 | ||||
| -rw-r--r-- | lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 34 |
2 files changed, 0 insertions, 38 deletions
diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h index 9d0d6cf6fd..3b3816a510 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -49,10 +49,6 @@ public: SmallVectorImpl<MCFixup> &Fixups) const { return 0; } - virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const { - return 0; - } }; } // End namespace llvm diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index b4bdb25289..8acc78fdbc 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -92,10 +92,6 @@ public: virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const; - /// \brief Encoding for SMRD indexed loads - virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixup) const; - /// \brief Post-Encoder method for VOP instructions virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; @@ -183,36 +179,6 @@ unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI, return GPRAlign(MI, OpNo, 2); } -#define SMRD_OFFSET_MASK 0xff -#define SMRD_IMM_SHIFT 8 -#define SMRD_SBASE_MASK 0x3f -#define SMRD_SBASE_SHIFT 9 -/// This function is responsibe for encoding the offset -/// and the base ptr for SMRD instructions it should return a bit string in -/// this format: -/// -/// OFFSET = bits{7-0} -/// IMM = bits{8} -/// SBASE = bits{14-9} -/// -uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixup) const { - uint32_t Encoding; - - const MCOperand &OffsetOp = MI.getOperand(OpNo + 1); - - //XXX: Use this function for SMRD loads with register offsets - assert(OffsetOp.isImm()); - - Encoding = - (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK) - | (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit - | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT) - ; - - return Encoding; -} - //===----------------------------------------------------------------------===// // Post Encoder Callbacks //===----------------------------------------------------------------------===// |