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authorBill Wendling <isanbard@gmail.com>2013-06-07 20:28:55 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 20:28:55 +0000
commitb5632b5b456db647b42239cbd4d8b58c82290c4e (patch)
tree4662bb108ed60bf4d5a2692aa7bc82d19342620e /lib/Target/R600/R600ControlFlowFinalizer.cpp
parentce961477be78b3945e6ec4b7e22066f237a89846 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600ControlFlowFinalizer.cpp')
-rw-r--r--lib/Target/R600/R600ControlFlowFinalizer.cpp16
1 files changed, 9 insertions, 7 deletions
diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp
index f229613307..3d448bf3d3 100644
--- a/lib/Target/R600/R600ControlFlowFinalizer.cpp
+++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp
@@ -49,7 +49,7 @@ private:
static char ID;
const R600InstrInfo *TII;
- const R600RegisterInfo &TRI;
+ const R600RegisterInfo *TRI;
unsigned MaxFetchInst;
const AMDGPUSubtarget &ST;
@@ -122,8 +122,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
DstMI = Reg;
else
- DstMI = TRI.getMatchingSuperReg(Reg,
- TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
+ DstMI = TRI->getMatchingSuperReg(Reg,
+ TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
if (MO.isUse()) {
@@ -131,8 +131,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
SrcMI = Reg;
else
- SrcMI = TRI.getMatchingSuperReg(Reg,
- TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
+ SrcMI = TRI->getMatchingSuperReg(Reg,
+ TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
}
@@ -318,14 +318,16 @@ private:
public:
R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())),
- TRI(TII->getRegisterInfo()),
+ TII (0), TRI(0),
ST(tm.getSubtarget<AMDGPUSubtarget>()) {
const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
MaxFetchInst = ST.getTexVTXClauseSize();
}
virtual bool runOnMachineFunction(MachineFunction &MF) {
+ TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
+ TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
+
unsigned MaxStack = 0;
unsigned CurrentStack = 0;
bool HasPush = false;