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authorVincent Lejeune <vljn@ovi.com>2013-04-30 00:13:39 +0000
committerVincent Lejeune <vljn@ovi.com>2013-04-30 00:13:39 +0000
commit631591e6f3e5119d8a8b1c853279bc4ac7ace4a0 (patch)
tree9ddfd9cbe4a94173530cc4ed76fd44b22948c4a9 /lib/Target/R600/R600InstrInfo.h
parent7d8ea50b93916b3dde07cc017d738b3fff43d3c7 (diff)
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R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600InstrInfo.h')
-rw-r--r--lib/Target/R600/R600InstrInfo.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h
index dbae90013d..2146788604 100644
--- a/lib/Target/R600/R600InstrInfo.h
+++ b/lib/Target/R600/R600InstrInfo.h
@@ -33,6 +33,7 @@ namespace llvm {
class R600InstrInfo : public AMDGPUInstrInfo {
private:
const R600RegisterInfo RI;
+ const AMDGPUSubtarget &ST;
int getBranchInstr(const MachineOperand &op) const;
@@ -53,6 +54,11 @@ namespace llvm {
/// \returns true if this \p Opcode represents an ALU instruction.
bool isALUInstr(unsigned Opcode) const;
+ bool usesVertexCache(unsigned Opcode) const;
+ bool usesVertexCache(const MachineInstr *MI) const;
+ bool usesTextureCache(unsigned Opcode) const;
+ bool usesTextureCache(const MachineInstr *MI) const;
+
bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
bool canBundle(const std::vector<MachineInstr *> &) const;