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author | Tom Stellard <thomas.stellard@amd.com> | 2012-12-11 21:25:42 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-11 21:25:42 +0000 |
commit | f98f2ce29e6e2996fa58f38979143eceaa818335 (patch) | |
tree | 86dffe7414e6657874db8ac36e5ddcf7d41b2d9c /lib/Target/R600/R600Schedule.td | |
parent | 57ac1f458a754f30cf500410b438fb260f9b8fe5 (diff) | |
download | llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.tar.gz llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.tar.bz2 llvm-f98f2ce29e6e2996fa58f38979143eceaa818335.tar.xz |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600Schedule.td')
-rw-r--r-- | lib/Target/R600/R600Schedule.td | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/lib/Target/R600/R600Schedule.td b/lib/Target/R600/R600Schedule.td new file mode 100644 index 0000000000..7ede181c51 --- /dev/null +++ b/lib/Target/R600/R600Schedule.td @@ -0,0 +1,36 @@ +//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction +// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS +// slot has been removed. +// +//===----------------------------------------------------------------------===// + + +def ALU_X : FuncUnit; +def ALU_Y : FuncUnit; +def ALU_Z : FuncUnit; +def ALU_W : FuncUnit; +def TRANS : FuncUnit; + +def AnyALU : InstrItinClass; +def VecALU : InstrItinClass; +def TransALU : InstrItinClass; + +def R600_EG_Itin : ProcessorItineraries < + [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], + [], + [ + InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>, + InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>, + InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>, + InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> + ] +>; |