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author | Christian Konig <christian.koenig@amd.com> | 2013-04-10 08:39:16 +0000 |
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committer | Christian Konig <christian.koenig@amd.com> | 2013-04-10 08:39:16 +0000 |
commit | 4d0e8a8a3e2e5b98f598acad4d57452b99d52e74 (patch) | |
tree | b02888c7d78ff0841f6ab4668192c8b754d2defd /lib/Target/R600/SIInstrInfo.cpp | |
parent | 84a775d8e3d5a3765e01db4b454f849ed8be99be (diff) | |
download | llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.tar.gz llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.tar.bz2 llvm-4d0e8a8a3e2e5b98f598acad4d57452b99d52e74.tar.xz |
R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.cpp')
-rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 0bfcef562f..9a04c609b6 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -58,6 +58,10 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0 }; + const int16_t Sub0_2[] = { + AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0 + }; + const int16_t Sub0_1[] = { AMDGPU::sub0, AMDGPU::sub1, 0 }; @@ -125,6 +129,11 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opcode = AMDGPU::V_MOV_B32_e32; SubIndices = Sub0_1; + } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) { + assert(AMDGPU::VReg_96RegClass.contains(SrcReg)); + Opcode = AMDGPU::V_MOV_B32_e32; + SubIndices = Sub0_2; + } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) { assert(AMDGPU::VReg_128RegClass.contains(SrcReg) || AMDGPU::SReg_128RegClass.contains(SrcReg)); |