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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:17 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:17 +0000 |
| commit | df4626ef15ba0eb5f571a3ee6314e5c388258927 (patch) | |
| tree | de05514081bc4a18624a799d774784522df62a98 /lib/Target/R600/SIInstrInfo.cpp | |
| parent | b49fb7bcd5001567d2da06f6a6e1c7ba79649e1b (diff) | |
| download | llvm-df4626ef15ba0eb5f571a3ee6314e5c388258927.tar.gz llvm-df4626ef15ba0eb5f571a3ee6314e5c388258927.tar.bz2 llvm-df4626ef15ba0eb5f571a3ee6314e5c388258927.tar.xz | |
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.cpp')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 551ae8683e..9bb4ad9abc 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -15,6 +15,7 @@ #include "SIInstrInfo.h" #include "AMDGPUTargetMachine.h" +#include "SIDefines.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCInstrDesc.h" @@ -224,6 +225,10 @@ SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { return RC != &AMDGPU::EXECRegRegClass; } +int SIInstrInfo::isMIMG(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::MIMG; +} + //===----------------------------------------------------------------------===// // Indirect addressing callbacks //===----------------------------------------------------------------------===// |