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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
| commit | 38d5e1c36d954f1ff6489f58efd1d4865217cf9b (patch) | |
| tree | 451454dd8bf6ea5ec2f3ea021da2c7f6de4a928a /lib/Target/R600/SIInstructions.td | |
| parent | 636298ba64fd07d4ddcae6005e7fc1db43eb5335 (diff) | |
| download | llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.gz llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.bz2 llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.xz | |
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInstructions.td')
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index b20d7c0533..d4e0b03370 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1525,16 +1525,6 @@ foreach Index = 0-15 in { >; } -def : Vector1_Build <v1i32, i32, VReg_32>; -def : Vector2_Build <v2i32, i32>; -def : Vector2_Build <v2f32, f32>; -def : Vector4_Build <v4i32, i32>; -def : Vector4_Build <v4f32, f32>; -def : Vector8_Build <v8i32, i32>; -def : Vector8_Build <v8f32, f32>; -def : Vector16_Build <v16i32, i32>; -def : Vector16_Build <v16f32, f32>; - def : BitConvert <i32, f32, SReg_32>; def : BitConvert <i32, f32, VReg_32>; |