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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:30 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:30 +0000 |
| commit | e9ba1830df2efef3da113a740909195e839ebd36 (patch) | |
| tree | 93e772de9a442b7fa9fe4e13b73b3d8a8223a3cc /lib/Target/R600/SIRegisterInfo.td | |
| parent | e25e490793241e471036c3e2f969ce6a068e5ce1 (diff) | |
| download | llvm-e9ba1830df2efef3da113a740909195e839ebd36.tar.gz llvm-e9ba1830df2efef3da113a740909195e839ebd36.tar.bz2 llvm-e9ba1830df2efef3da113a740909195e839ebd36.tar.xz | |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 7f1fec086d..ab36b8733d 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -137,9 +137,7 @@ def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add SGPR_32, M0, EXEC_LO, EXEC_HI) >; -def SReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add SGPR_64, VCC, EXEC)>; - -def SReg_1 : RegisterClass<"AMDGPU", [i1], 1, (add VCC, SGPR_64, EXEC)>; +def SReg_64 : RegisterClass<"AMDGPU", [i1, i64], 64, (add SGPR_64, VCC, EXEC)>; def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>; @@ -178,7 +176,7 @@ def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>; // [SV]Src_* operands can have either an immediate or an register def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>; -def SSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add SReg_64)>; +def SSrc_64 : RegisterClass<"AMDGPU", [i1, i64], 64, (add SReg_64)>; def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>; |