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author | Aaron Ballman <aaron@aaronballman.com> | 2013-10-29 20:40:52 +0000 |
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committer | Aaron Ballman <aaron@aaronballman.com> | 2013-10-29 20:40:52 +0000 |
commit | 5203b7773e29b36e38aac0ce9358fa7843065681 (patch) | |
tree | 2f6d7f3ac5acfd4d630f413e53b3f5fc628d6c5a /lib/Target/R600 | |
parent | 615a279f81e08e9c63fd5e411b33d39bfe593314 (diff) | |
download | llvm-5203b7773e29b36e38aac0ce9358fa7843065681.tar.gz llvm-5203b7773e29b36e38aac0ce9358fa7843065681.tar.bz2 llvm-5203b7773e29b36e38aac0ce9358fa7843065681.tar.xz |
Removing a switch statement that contains only a default label. This resolves an MSVC warning. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193649 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/AMDGPUInstrInfo.cpp | 53 |
1 files changed, 25 insertions, 28 deletions
diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index 434c91a523..592dcbf4ff 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -121,36 +121,33 @@ AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const { MachineBasicBlock *MBB = MI->getParent(); - switch(MI->getOpcode()) { - default: - if (isRegisterLoad(*MI)) { - unsigned RegIndex = MI->getOperand(2).getImm(); - unsigned Channel = MI->getOperand(3).getImm(); - unsigned Address = calculateIndirectAddress(RegIndex, Channel); - unsigned OffsetReg = MI->getOperand(1).getReg(); - if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { - buildMovInstr(MBB, MI, MI->getOperand(0).getReg(), - getIndirectAddrRegClass()->getRegister(Address)); - } else { - buildIndirectRead(MBB, MI, MI->getOperand(0).getReg(), - Address, OffsetReg); - } - } else if (isRegisterStore(*MI)) { - unsigned RegIndex = MI->getOperand(2).getImm(); - unsigned Channel = MI->getOperand(3).getImm(); - unsigned Address = calculateIndirectAddress(RegIndex, Channel); - unsigned OffsetReg = MI->getOperand(1).getReg(); - if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { - buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address), - MI->getOperand(0).getReg()); - } else { - buildIndirectWrite(MBB, MI, MI->getOperand(0).getReg(), - calculateIndirectAddress(RegIndex, Channel), - OffsetReg); - } + if (isRegisterLoad(*MI)) { + unsigned RegIndex = MI->getOperand(2).getImm(); + unsigned Channel = MI->getOperand(3).getImm(); + unsigned Address = calculateIndirectAddress(RegIndex, Channel); + unsigned OffsetReg = MI->getOperand(1).getReg(); + if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { + buildMovInstr(MBB, MI, MI->getOperand(0).getReg(), + getIndirectAddrRegClass()->getRegister(Address)); + } else { + buildIndirectRead(MBB, MI, MI->getOperand(0).getReg(), + Address, OffsetReg); + } + } else if (isRegisterStore(*MI)) { + unsigned RegIndex = MI->getOperand(2).getImm(); + unsigned Channel = MI->getOperand(3).getImm(); + unsigned Address = calculateIndirectAddress(RegIndex, Channel); + unsigned OffsetReg = MI->getOperand(1).getReg(); + if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { + buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address), + MI->getOperand(0).getReg()); } else { - return false; + buildIndirectWrite(MBB, MI, MI->getOperand(0).getReg(), + calculateIndirectAddress(RegIndex, Channel), + OffsetReg); } + } else { + return false; } MBB->erase(MI); |