diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2013-11-12 16:26:47 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-11-12 16:26:47 +0000 |
| commit | 837dd95d6c8cb4f23df4e54eac027eb289991629 (patch) | |
| tree | 25cc0e0b2ddf743f66525d586104563a06207d9c /lib/Target/R600 | |
| parent | 9e2838e29b0820afc35f6ef2d465d4aca9ed402a (diff) | |
| download | llvm-837dd95d6c8cb4f23df4e54eac027eb289991629.tar.gz llvm-837dd95d6c8cb4f23df4e54eac027eb289991629.tar.bz2 llvm-837dd95d6c8cb4f23df4e54eac027eb289991629.tar.xz | |
R600: Reenable llvm.R600.load.input/interp.input for compatibility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 45 | ||||
| -rw-r--r-- | lib/Target/R600/R600Intrinsics.td | 2 |
2 files changed, 47 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 336a2991d1..5bb8129677 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -554,6 +554,51 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const SDLoc DL(Op); switch(IntrinsicID) { default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); + case AMDGPUIntrinsic::R600_load_input: { + int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); + unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + MRI.addLiveIn(Reg); + return DAG.getCopyFromReg(DAG.getEntryNode(), + SDLoc(DAG.getEntryNode()), Reg, VT); + } + + case AMDGPUIntrinsic::R600_interp_input: { + int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); + int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue(); + MachineSDNode *interp; + if (ijb < 0) { + const MachineFunction &MF = DAG.getMachineFunction(); + const R600InstrInfo *TII = + static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo()); + interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, + MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32)); + return DAG.getTargetExtractSubreg( + TII->getRegisterInfo().getSubRegFromChannel(slot % 4), + DL, MVT::f32, SDValue(interp, 0)); + } + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb); + unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1); + MRI.addLiveIn(RegisterI); + MRI.addLiveIn(RegisterJ); + SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(), + SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32); + SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(), + SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32); + + if (slot % 4 < 2) + interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, + MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32), + RegisterJNode, RegisterINode); + else + interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, + MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32), + RegisterJNode, RegisterINode); + return SDValue(interp, slot % 2); + } case AMDGPUIntrinsic::R600_interp_xy: case AMDGPUIntrinsic::R600_interp_zw: { int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); diff --git a/lib/Target/R600/R600Intrinsics.td b/lib/Target/R600/R600Intrinsics.td index cd0b4193c3..9681747006 100644 --- a/lib/Target/R600/R600Intrinsics.td +++ b/lib/Target/R600/R600Intrinsics.td @@ -39,6 +39,8 @@ let TargetPrefix = "R600", isTarget = 1 in { llvm_i32_ty // coord_type_w ], [IntrNoMem]>; + def int_R600_load_input : + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>; def int_R600_interp_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_R600_interp_const : |