First step towards V9 instructions in the V8 backend, two conditional move

patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 6 deletions

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index f767def153..b08a752a61 100644
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -1,10 +1,4 @@
 
-Meta TODO list:
-1. Create a new DAG -> DAG instruction selector, by adding patterns to the
-   instructions.
-2. ???
-3. profit!
-
 To-do
 -----
 
@@ -12,4 +6,5 @@ To-do
   address all of the time.
 * We can fold small constant offsets into the %hi/%lo references to constant
   pool addresses as well.
+* When in V9 mode, register allocate %icc[0-3].