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author | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-22 21:38:42 +0000 |
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committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-22 21:38:42 +0000 |
commit | c42077d37194a1872dc402522d4d7a0e81f83047 (patch) | |
tree | 6042a2a00b5794c163e6e71bd9b4666db284d708 /lib/Target/Sparc/SparcInstrFormats.td | |
parent | 31b5edd2e996cbf28db7630a38d1a24dc13ec9a4 (diff) | |
download | llvm-c42077d37194a1872dc402522d4d7a0e81f83047.tar.gz llvm-c42077d37194a1872dc402522d4d7a0e81f83047.tar.bz2 llvm-c42077d37194a1872dc402522d4d7a0e81f83047.tar.xz |
Combine the F2 and F3 instruction classes into one file for simplicity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrFormats.td')
-rw-r--r-- | lib/Target/Sparc/SparcInstrFormats.td | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td new file mode 100644 index 0000000000..cef4ecb033 --- /dev/null +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -0,0 +1,97 @@ +//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Format #2 instruction classes in the SparcV8 +//===----------------------------------------------------------------------===// + +class F2 : InstV8 { // Format 2 instructions + bits<3> op2; + bits<22> imm22; + let op = 0; // op = 0 + let Inst{24-22} = op2; + let Inst{21-0} = imm22; +} + +// Specific F2 classes: SparcV8 manual, page 44 +// +class F2_1<bits<3> op2Val, string name> : F2 { + bits<5> rd; + bits<22> imm; + + let op2 = op2Val; + let Name = name; + + let Inst{29-25} = rd; +} + +class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 { + bits<4> cond; + bit annul = 0; // currently unused + + let cond = condVal; + let op2 = op2Val; + let Name = name; + + let Inst{29} = annul; + let Inst{28-25} = cond; +} + +//===----------------------------------------------------------------------===// +// Format #3 instruction classes in the SparcV8 +//===----------------------------------------------------------------------===// + +class F3 : InstV8 { + bits<5> rd; + bits<6> op3; + bits<5> rs1; + let op{1} = 1; // Op = 2 or 3 + let Inst{29-25} = rd; + let Inst{24-19} = op3; + let Inst{18-14} = rs1; +} + +// Specific F3 classes: SparcV8 manual, page 44 +// +class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = asi; // address space identifier + let Inst{4-0} = rs2; +} + +class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 { + bits<13> simm13; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; +} + +// floating-point +class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13-5} = opfval; // fp opcode + let Inst{4-0} = rs2; +} |