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authorChris Lattner <sabre@nondot.org>2005-12-18 08:21:00 +0000
committerChris Lattner <sabre@nondot.org>2005-12-18 08:21:00 +0000
commiteee99bd459ab17a498d076f27de313398b9d3d4d (patch)
tree0983351ba86ebf178c19b8df4d0169a92d93494c /lib/Target/Sparc/SparcInstrFormats.td
parent3308449afc6f1b8b8536e544e53bc6751c91b4e3 (diff)
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Push ops list, asm string, and pattern all the way up to InstV8. Move the
InstV8 class to the InstrFormats file where it belongs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrFormats.td')
-rw-r--r--lib/Target/Sparc/SparcInstrFormats.td51
1 files changed, 24 insertions, 27 deletions
diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td
index 1e73121372..9b15aeed50 100644
--- a/lib/Target/Sparc/SparcInstrFormats.td
+++ b/lib/Target/Sparc/SparcInstrFormats.td
@@ -7,11 +7,26 @@
//
//===----------------------------------------------------------------------===//
+class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
+ field bits<32> Inst;
+
+ let Namespace = "V8";
+
+ bits<2> op;
+ let Inst{31-30} = op; // Top two bits are the 'op' field
+
+ dag OperandList = ops;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+}
+
//===----------------------------------------------------------------------===//
// Format #2 instruction classes in the SparcV8
//===----------------------------------------------------------------------===//
-class F2 : InstV8 { // Format 2 instructions
+// Format 2 instructions
+class F2<dag ops, string asmstr, list<dag> pattern>
+ : InstV8<ops, asmstr, pattern> {
bits<3> op2;
bits<22> imm22;
let op = 0; // op = 0
@@ -21,27 +36,20 @@ class F2 : InstV8 { // Format 2 instructions
// Specific F2 classes: SparcV8 manual, page 44
//
-class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
+class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
+ : F2<ops, asmstr, pattern> {
bits<5> rd;
- dag OperandList = ops;
- let AsmString = asmstr;
- let Pattern = pattern;
-
let op2 = op2Val;
let Inst{29-25} = rd;
}
class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
- list<dag> pattern> : F2 {
+ list<dag> pattern> : F2<ops, asmstr, pattern> {
bits<4> cond;
bit annul = 0; // currently unused
- dag OperandList = ops;
- let AsmString = asmstr;
- let Pattern = pattern;
-
let cond = condVal;
let op2 = op2Val;
@@ -53,7 +61,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
// Format #3 instruction classes in the SparcV8
//===----------------------------------------------------------------------===//
-class F3 : InstV8 {
+class F3<dag ops, string asmstr, list<dag> pattern>
+ : InstV8<ops, asmstr, pattern> {
bits<5> rd;
bits<6> op3;
bits<5> rs1;
@@ -66,14 +75,10 @@ class F3 : InstV8 {
// Specific F3 classes: SparcV8 manual, page 44
//
class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
- string asmstr, list<dag> pattern> : F3 {
+ string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
bits<8> asi = 0; // asi not currently used in SparcV8
bits<5> rs2;
- dag OperandList = ops;
- let AsmString = asmstr;
- let Pattern = pattern;
-
let op = opVal;
let op3 = op3val;
@@ -83,13 +88,9 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
}
class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
- string asmstr, list<dag> pattern> : F3 {
+ string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
bits<13> simm13;
- dag OperandList = ops;
- let AsmString = asmstr;
- let Pattern = pattern;
-
let op = opVal;
let op3 = op3val;
@@ -99,13 +100,9 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
// floating-point
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
- string asmstr, list<dag> pattern> : F3 {
+ string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
bits<5> rs2;
- dag OperandList = ops;
- let AsmString = asmstr;
- let Pattern = pattern;
-
let op = opVal;
let op3 = op3val;