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authorEvan Cheng <evan.cheng@apple.com>2007-10-05 01:32:41 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-10-05 01:32:41 +0000
commit66f0f640820b61cf9db814b6d187bae9faf7279c (patch)
tree4d3b6ebbdf3bc1e7a4c69c6aa7d4a64931ff8820 /lib/Target/Sparc/SparcRegisterInfo.h
parent39305cf55363046162c5a992f96f26d607a204e5 (diff)
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- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcRegisterInfo.h')
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index a0e6fc239d..39cf6160d6 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -35,11 +35,21 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
+ void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ SmallVector<MachineOperand,4> Addr,
+ const TargetRegisterClass *RC,
+ SmallVector<MachineInstr*, 4> &NewMIs) const;
+
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
+ void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVector<MachineOperand,4> Addr,
+ const TargetRegisterClass *RC,
+ SmallVector<MachineInstr*, 4> &NewMIs) const;
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,