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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-29 04:46:31 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-29 04:46:31 +0000 |
| commit | 530086925695f074b0e1e38a0d88ee6a4c91c54c (patch) | |
| tree | 3f0208636976c50c5a15795252265ff6a59225e6 /lib/Target/Sparc/SparcRegisterInfo.td | |
| parent | 0cf4adbcef584cb56254e253b47315b4c3d073ec (diff) | |
| download | llvm-530086925695f074b0e1e38a0d88ee6a4c91c54c.tar.gz llvm-530086925695f074b0e1e38a0d88ee6a4c91c54c.tar.bz2 llvm-530086925695f074b0e1e38a0d88ee6a4c91c54c.tar.xz | |
[Sparc] Add support for leaf functions in sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182822 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcRegisterInfo.td')
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 04e92e747e..d1edcb6de1 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -144,20 +144,10 @@ def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; // register class for that. The i64 type is included here to allow i64 patterns // using the integer instructions. def IntRegs : RegisterClass<"SP", [i32, i64], 32, - (add I0, I1, I2, I3, I4, I5, - G1, - G2, G3, G4, // OK for use only in - // applications, not libraries. - G5, // OK for use in 64 bit mode. - L0, L1, L2, L3, L4, L5, L6, L7, - O0, O1, O2, O3, O4, O5, O7, - // Non-allocatable regs: - O6, // stack ptr - I6, // frame ptr - I7, // return address - G0, // constant zero - G6, G7 // reserved for kernel - )>; + (add (sequence "I%u", 0, 7), + (sequence "G%u", 0, 7), + (sequence "L%u", 0, 7), + (sequence "O%u", 0, 7))>; // Register class for 64-bit mode, with a 64-bit spill slot size. // These are the same as the 32-bit registers, so TableGen will consider this |