Merging r195473:

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r195473 | rsandifo | 2013-11-22 17:28:28 +0000 (Fri, 22 Nov 2013) | 10 lines

[SystemZ] Fix TMHH and TMHL usage for z10 with -O0

I've no idea why I decided to handle TMxx differently from all the other
high/low logic operations, but it was a stupid thing to do.  The high
registers aren't available as separate 32-bit registers on z10,
so subreg_h32 can't be used on a GR64 there.

I've normally been testing with z196 and with -O3 and so hadn't noticed
this until now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195474 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 22 insertions, 8 deletions

diff --git a/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 75efdb0941..75cbda4958 100644
--- a/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -29,19 +29,29 @@ using namespace llvm;
 // Return an RI instruction like MI with opcode Opcode, but with the
 // GR64 register operands turned into GR32s.
 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
-  return MCInstBuilder(Opcode)
-    .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
-    .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
-    .addImm(MI->getOperand(2).getImm());
+  if (MI->isCompare())
+    return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
+      .addImm(MI->getOperand(1).getImm());
+  else
+    return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
+      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
+      .addImm(MI->getOperand(2).getImm());
 }
 
 // Return an RI instruction like MI with opcode Opcode, but with the
 // GR64 register operands turned into GRH32s.
 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
-  return MCInstBuilder(Opcode)
-    .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
-    .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
-    .addImm(MI->getOperand(2).getImm());
+  if (MI->isCompare())
+    return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
+      .addImm(MI->getOperand(1).getImm());
+  else
+    return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
+      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
+      .addImm(MI->getOperand(2).getImm());
 }
 
 // Return an RI instruction like MI with opcode Opcode, but with the
@@ -112,6 +122,8 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
 
   LOWER_LOW(IILL);
   LOWER_LOW(IILH);
+  LOWER_LOW(TMLL);
+  LOWER_LOW(TMLH);
   LOWER_LOW(NILL);
   LOWER_LOW(NILH);
   LOWER_LOW(NILF);
@@ -127,6 +139,8 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
 
   LOWER_HIGH(IIHL);
   LOWER_HIGH(IIHH);
+  LOWER_HIGH(TMHL);
+  LOWER_HIGH(TMHH);
   LOWER_HIGH(NIHL);
   LOWER_HIGH(NIHH);
   LOWER_HIGH(NIHF);