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author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:03:41 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:03:41 +0000 |
commit | 3166a9ac5c81621bb7f58f8cd4311694af26fa29 (patch) | |
tree | 81c0b59664723f430e1fcd93d0742d238f6bf81b /lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | |
parent | 501f55d84159c409bb902361812bc1912a798026 (diff) | |
download | llvm-3166a9ac5c81621bb7f58f8cd4311694af26fa29.tar.gz llvm-3166a9ac5c81621bb7f58f8cd4311694af26fa29.tar.bz2 llvm-3166a9ac5c81621bb7f58f8cd4311694af26fa29.tar.xz |
32-bit ri addressing mode has only 12-bit displacement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75973 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelDAGToDAG.cpp')
-rw-r--r-- | lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 3e1cc3c544..603cfecb59 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -105,6 +105,8 @@ namespace { #include "SystemZGenDAGISel.inc" private: + bool SelectAddrRI32(const SDValue& Op, SDValue& Addr, + SDValue &Base, SDValue &Disp); bool SelectAddrRI(const SDValue& Op, SDValue& Addr, SDValue &Base, SDValue &Disp); bool SelectAddrRRI(SDValue Op, SDValue Addr, @@ -153,6 +155,88 @@ static bool isImmSExt20(SDValue Op, int64_t &Imm) { return isImmSExt20(Op.getNode(), Imm); } +/// isImmSExt12 - This method tests to see if the node is either a 32-bit +/// or 64-bit immediate, and if the value can be accurately represented as a +/// zero extension from a 12-bit value. If so, this returns true and the +/// immediate. +static bool isImmZExt12(SDNode *N, uint64_t &Imm) { + if (N->getOpcode() != ISD::Constant) + return false; + + uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); + if (Val <= 0xFFF) { + Imm = Val; + return true; + } + + return false; +} + +static bool isImmZExt12(SDValue Op, uint64_t &Imm) { + return isImmZExt12(Op.getNode(), Imm); +} + +/// Returns true if the address can be represented by a base register plus +/// an unsigned 12-bit displacement [r+imm]. +bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr, + SDValue &Base, SDValue &Disp) { + // FIXME dl should come from parent load or store, not from address + DebugLoc dl = Addr.getDebugLoc(); + MVT VT = Addr.getValueType(); + + if (Addr.getOpcode() == ISD::ADD) { + uint64_t Imm = 0; + if (isImmZExt12(Addr.getOperand(1), Imm)) { + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + if (FrameIndexSDNode *FI = + dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT); + } else { + Base = Addr.getOperand(0); + } + return true; // [r+i] + } + } else if (Addr.getOpcode() == ISD::OR) { + uint64_t Imm = 0; + if (isImmZExt12(Addr.getOperand(1), Imm)) { + // If this is an or of disjoint bitfields, we can codegen this as an add + // (for better address arithmetic) if the LHS and RHS of the OR are + // provably disjoint. + APInt LHSKnownZero, LHSKnownOne; + CurDAG->ComputeMaskedBits(Addr.getOperand(0), + APInt::getAllOnesValue(Addr.getOperand(0) + .getValueSizeInBits()), + LHSKnownZero, LHSKnownOne); + + if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) { + // If all of the bits are known zero on the LHS or RHS, the add won't + // carry. + Base = Addr.getOperand(0); + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + return true; + } + } + } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) { + // Loading from a constant address. + + // If this address fits entirely in a 12-bit zext immediate field, codegen + // this as "d(r0)" + uint64_t Imm; + if (isImmZExt12(CN, Imm)) { + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + Base = CurDAG->getRegister(0, VT); + return true; + } + } + + Disp = CurDAG->getTargetConstant(0, MVT::i64); + if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT); + else + Base = Addr; + return true; // [r+0] +} + /// Returns true if the address can be represented by a base register plus /// a signed 20-bit displacement [r+imm]. bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr, |