diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:14:54 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:14:54 +0000 |
| commit | e3a7f7a2b20ad791626f58e16d76a514ea66b62b (patch) | |
| tree | c49050e22582d5f8ac63553739654c29798a74a4 /lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | |
| parent | 0a42d2b4376526dbef25834b29a39fa684f9a902 (diff) | |
| download | llvm-e3a7f7a2b20ad791626f58e16d76a514ea66b62b.tar.gz llvm-e3a7f7a2b20ad791626f58e16d76a514ea66b62b.tar.bz2 llvm-e3a7f7a2b20ad791626f58e16d76a514ea66b62b.tar.xz | |
Remove redundand register move
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelDAGToDAG.cpp')
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 3df814e1bb..c63376683a 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -645,7 +645,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { default: assert(0 && "Unsupported VT!"); case MVT::i32: Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; - ClrOpc = SystemZ::MOV32ri16; + ClrOpc = SystemZ::MOV64Pr0_even; ResVT = MVT::v2i32; break; case MVT::i64: @@ -669,15 +669,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { CurDAG->getTargetConstant(subreg_odd, MVT::i32)); // Zero out even subreg, if needed - if (ClrOpc) { - SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT, - CurDAG->getTargetConstant(0, MVT::i32)); - Dividend = - CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, - SDValue(Dividend, 0), - SDValue(ZeroHi, 0), - CurDAG->getTargetConstant(subreg_even, MVT::i32)); - } + if (ClrOpc) + Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); SDNode *Result; SDValue DivVal = SDValue(Dividend, 0); @@ -736,12 +729,12 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { default: assert(0 && "Unsupported VT!"); case MVT::i32: Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; - ClrOpc = SystemZ::MOV32ri16; + ClrOpc = SystemZ::MOV64Pr0_even; ResVT = MVT::v2i32; break; case MVT::i64: Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; - ClrOpc = SystemZ::MOV64ri16; + ClrOpc = SystemZ::MOV128r0_even; ResVT = MVT::v2i64; break; } @@ -760,15 +753,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDValue(Tmp, 0), SDValue(Dividend, 0), CurDAG->getTargetConstant(subreg_odd, MVT::i32)); - // Zero out even subreg, if needed - SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT, - CurDAG->getTargetConstant(0, - MVT::i32)); - Dividend = - CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, - SDValue(Dividend, 0), - SDValue(ZeroHi, 0), - CurDAG->getTargetConstant(subreg_even, MVT::i32)); + // Zero out even subreg + Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); SDValue DivVal = SDValue(Dividend, 0); SDNode *Result; |