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authorOwen Anderson <resistor@mac.com>2009-08-11 20:47:22 +0000
committerOwen Anderson <resistor@mac.com>2009-08-11 20:47:22 +0000
commit825b72b0571821bf2d378749f69d6c4cfb52d2f9 (patch)
tree12e46abe2504796792a4fe0f5dde4c94213fdddc /lib/Target/SystemZ/SystemZISelLowering.cpp
parent0ad7f9bb2f806387e53ffeaf6a564b9a80b962af (diff)
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Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelLowering.cpp')
-rw-r--r--lib/Target/SystemZ/SystemZISelLowering.cpp168
1 files changed, 84 insertions, 84 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 6ffb434bbf..279e22b653 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -44,14 +44,14 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
RegInfo = TM.getRegisterInfo();
// Set up the register classes.
- addRegisterClass(EVT::i32, SystemZ::GR32RegisterClass);
- addRegisterClass(EVT::i64, SystemZ::GR64RegisterClass);
- addRegisterClass(EVT::v2i32,SystemZ::GR64PRegisterClass);
- addRegisterClass(EVT::v2i64,SystemZ::GR128RegisterClass);
+ addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
+ addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
+ addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
+ addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
if (!UseSoftFloat) {
- addRegisterClass(EVT::f32, SystemZ::FP32RegisterClass);
- addRegisterClass(EVT::f64, SystemZ::FP64RegisterClass);
+ addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
+ addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
addLegalFPImmediate(APFloat(+0.0)); // lzer
addLegalFPImmediate(APFloat(+0.0f)); // lzdr
@@ -63,92 +63,92 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
computeRegisterProperties();
// Set shifts properties
- setShiftAmountType(EVT::i64);
+ setShiftAmountType(MVT::i64);
// Provide all sorts of operation actions
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D);
setSchedulingPreference(SchedulingForLatency);
setBooleanContents(ZeroOrOneBooleanContent);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::i64, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
-
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIV, EVT::i64, Expand);
- setOperationAction(ISD::UDIV, EVT::i64, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
-
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
-
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i64, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i64, Expand);
- setOperationAction(ISD::CTLZ, EVT::i32, Promote);
- setOperationAction(ISD::CTLZ, EVT::i64, Legal);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i64, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Promote);
+ setOperationAction(ISD::CTLZ, MVT::i64, Legal);
// FIXME: Can we lower these 2 efficiently?
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::i64, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::i64, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::i64, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::i64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// Funny enough: we don't have 64-bit signed versions of these stuff, but have
// unsigned.
- setOperationAction(ISD::MULHS, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::MULHS, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
// Lower some FP stuff
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FSIN, EVT::f64, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FSIN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
// We have only 64-bit bitconverts
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
@@ -242,21 +242,21 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
if (VA.isRegLoc()) {
// Arguments passed in registers
TargetRegisterClass *RC;
- switch (LocVT.getSimpleVT()) {
+ switch (LocVT.getSimpleVT().SimpleTy) {
default:
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
- << LocVT.getSimpleVT()
+ << LocVT.getSimpleVT().SimpleTy
<< "\n";
#endif
llvm_unreachable(0);
- case EVT::i64:
+ case MVT::i64:
RC = SystemZ::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
RC = SystemZ::FP32RegisterClass;
break;
- case EVT::f64:
+ case MVT::f64:
RC = SystemZ::FP64RegisterClass;
break;
}
@@ -382,7 +382,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -404,7 +404,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -530,10 +530,10 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
}
if (Flag.getNode())
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
@@ -608,11 +608,11 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
break;
}
- SystemZCC = DAG.getConstant(TCC, EVT::i32);
+ SystemZCC = DAG.getConstant(TCC, MVT::i32);
DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
- dl, EVT::Flag, LHS, RHS);
+ dl, MVT::Flag, LHS, RHS);
}
@@ -641,7 +641,7 @@ SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
SDValue SystemZCC;
SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);