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author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:29:05 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:29:05 +0000 |
commit | c1a1e4adb72b547bbd80c7ad2594baa581542111 (patch) | |
tree | 6c6f663425608b525606f2e283a759ab07c0f5e3 /lib/Target/SystemZ/SystemZISelLowering.cpp | |
parent | 159ac63ba19f17f82df8975208bdad16ebd01c0f (diff) | |
download | llvm-c1a1e4adb72b547bbd80c7ad2594baa581542111.tar.gz llvm-c1a1e4adb72b547bbd80c7ad2594baa581542111.tar.bz2 llvm-c1a1e4adb72b547bbd80c7ad2594baa581542111.tar.xz |
i32 values are passed extended also on stack. Handle this in generic way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelLowering.cpp')
-rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 51a3e641d5..162f960f85 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -210,15 +210,16 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op, SmallVector<SDValue, 16> ArgValues; for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + SDValue ArgValue; CCValAssign &VA = ArgLocs[i]; + MVT LocVT = VA.getLocVT(); if (VA.isRegLoc()) { // Arguments passed in registers - MVT RegVT = VA.getLocVT(); TargetRegisterClass *RC; - switch (RegVT.getSimpleVT()) { + switch (LocVT.getSimpleVT()) { default: cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " - << RegVT.getSimpleVT() + << LocVT.getSimpleVT() << "\n"; abort(); case MVT::i64: @@ -234,37 +235,37 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op, unsigned VReg = RegInfo.createVirtualRegister(RC); RegInfo.addLiveIn(VA.getLocReg(), VReg); - SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT); - - // If this is an 8/16/32-bit value, it is really passed promoted to 64 - // bits. Insert an assert[sz]ext to capture this, then truncate to the - // right size. - if (VA.getLocInfo() == CCValAssign::SExt) - ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, - DAG.getValueType(VA.getValVT())); - else if (VA.getLocInfo() == CCValAssign::ZExt) - ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, - DAG.getValueType(VA.getValVT())); - - if (VA.getLocInfo() != CCValAssign::Full) - ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); - - ArgValues.push_back(ArgValue); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT); } else { // Sanity check assert(VA.isMemLoc()); // Create the nodes corresponding to a load from this parameter slot. // Create the frame index object for this incoming parameter... - int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, + int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, VA.getLocMemOffset()); // Create the SelectionDAG nodes corresponding to a load - //from this parameter + // from this parameter SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, - PseudoSourceValue::getFixedStack(FI), 0)); + ArgValue = DAG.getLoad(LocVT, dl, Root, FIN, + PseudoSourceValue::getFixedStack(FI), 0); } + + // If this is an 8/16/32-bit value, it is really passed promoted to 64 + // bits. Insert an assert[sz]ext to capture this, then truncate to the + // right size. + if (VA.getLocInfo() == CCValAssign::SExt) + ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, + DAG.getValueType(VA.getValVT())); + else if (VA.getLocInfo() == CCValAssign::ZExt) + ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, + DAG.getValueType(VA.getValVT())); + + if (VA.getLocInfo() != CCValAssign::Full) + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); + + ArgValues.push_back(ArgValue); } ArgValues.push_back(Root); |