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authorAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 14:14:33 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 14:14:33 +0000
commit0a42d2b4376526dbef25834b29a39fa684f9a902 (patch)
treec9c5317374d4b023274b75988216493ed967de0c /lib/Target/SystemZ/SystemZInstrInfo.td
parentd20af96f5b1c528af2dad59ac0c9cc4f2a968d2d (diff)
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Properly handle divides. As a bonus - implement memory versions of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.td')
-rw-r--r--lib/Target/SystemZ/SystemZInstrInfo.td86
1 files changed, 26 insertions, 60 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 17bf19c6d9..5a34d95e67 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -580,22 +580,34 @@ def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
"msgfr\t{$dst, $src2}",
[(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
-def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
- "dr\t{$dst, $src2}",
- []>;
-
-def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
- "dsgr\t{$dst, $src2}",
- []>;
-
-def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
- "dlr\t{$dst, $src2}",
- []>;
+def SDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
+ "dr\t{$dst, $src2}",
+ []>;
+def SDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
+ "dsgr\t{$dst, $src2}",
+ []>;
-def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
- "dlgr\t{$dst, $src2}",
- []>;
+def UDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
+ "dlr\t{$dst, $src2}",
+ []>;
+def UDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
+ "dlgr\t{$dst, $src2}",
+ []>;
+let mayLoad = 1 in {
+def SDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
+ "d\t{$dst, $src2}",
+ []>;
+def SDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
+ "dsg\t{$dst, $src2}",
+ []>;
+def UDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
+ "dl\t{$dst, $src2}",
+ []>;
+def UDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
+ "dlg\t{$dst, $src2}",
+ []>;
+} // mayLoad
} // isTwoAddress = 1
//===----------------------------------------------------------------------===//
@@ -790,51 +802,5 @@ def : Pat<(mulhu GR64:$src1, GR64:$src2),
GR64:$src2),
subreg_even)>;
-// divs
-// FIXME: Add memory versions
-def : Pat<(sdiv GR32:$src1, GR32:$src2),
- (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GR32:$src1, subreg_odd),
- GR32:$src2),
- subreg_odd)>;
-def : Pat<(sdiv GR64:$src1, GR64:$src2),
- (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
- GR64:$src1, subreg_odd),
- GR64:$src2),
- subreg_odd)>;
-def : Pat<(udiv GR32:$src1, GR32:$src2),
- (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GR32:$src1, subreg_odd),
- GR32:$src2),
- subreg_odd)>;
-def : Pat<(udiv GR64:$src1, GR64:$src2),
- (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
- GR64:$src1, subreg_odd),
- GR64:$src2),
- subreg_odd)>;
-
-// rems
-// FIXME: Add memory versions
-def : Pat<(srem GR32:$src1, GR32:$src2),
- (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GR32:$src1, subreg_odd),
- GR32:$src2),
- subreg_even)>;
-def : Pat<(srem GR64:$src1, GR64:$src2),
- (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
- GR64:$src1, subreg_odd),
- GR64:$src2),
- subreg_even)>;
-def : Pat<(urem GR32:$src1, GR32:$src2),
- (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GR32:$src1, subreg_odd),
- GR32:$src2),
- subreg_even)>;
-def : Pat<(urem GR64:$src1, GR64:$src2),
- (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
- GR64:$src1, subreg_odd),
- GR64:$src2),
- subreg_even)>;
-
def : Pat<(i32 imm:$src),
(EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;