diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:35:08 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:35:08 +0000 |
| commit | 9342d3180a4150c3becfda6216bb8ecef2794f44 (patch) | |
| tree | d0d1cca7b602b744a759314979ca9293a9f6a923 /lib/Target/SystemZ/SystemZInstrInfo.td | |
| parent | da308c9a67d044bdba181b8564f4ecfd65b94b43 (diff) | |
| download | llvm-9342d3180a4150c3becfda6216bb8ecef2794f44.tar.gz llvm-9342d3180a4150c3becfda6216bb8ecef2794f44.tar.bz2 llvm-9342d3180a4150c3becfda6216bb8ecef2794f44.tar.xz | |
Add another bunch of reg-imm patterns for add/or/and/xor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75922 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.td')
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 6008c49971..3443c4f82e 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -170,6 +170,10 @@ def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "aghi\t{$dst, $src2}", [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)), (implicit PSW)]>; +def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "agfi\t{$dst, $src2}", + [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)), + (implicit PSW)]>; let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y // FIXME: Provide proper encoding! @@ -191,6 +195,13 @@ def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nihh\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>; +// FIXME: these 2 instructions seem to require extimm facility +def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nilf\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>; +def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nihf\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>; let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y // FIXME: Provide proper encoding! @@ -198,6 +209,7 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "ogr\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; } + def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "oill\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; @@ -210,6 +222,13 @@ def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "oihh\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; +// FIXME: these 2 instructions seem to require extimm facility +def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oilf\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; +def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oihf\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; // FIXME: Provide proper encoding! def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), @@ -224,5 +243,13 @@ def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; } +// FIXME: these 2 instructions seem to require extimm facility +def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "xilf\t{$dst, $src2}", + [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>; +def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "xihf\t{$dst, $src2}", + [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>; + } // Defs = [PSW] } // isTwoAddress = 1 |