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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-30 12:01:35 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-30 12:01:35 +0000
commit16658af535ed09169cb1079a474334dbf1cb8dc7 (patch)
treed14dcdb1d6e4a0ec75163fa605c1c0e4744c18f8 /lib/Target/SystemZ
parente09bcad77c033392669b8d9cd3d93209064dfbc4 (diff)
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[SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ')
-rw-r--r--lib/Target/SystemZ/SystemZInstrInfo.td4
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index b93e863a95..4cd087540d 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -294,8 +294,6 @@ let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
- def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
- Requires<[FeatureHighWord]>;
def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
// These instructions are split after register allocation, so we don't
@@ -328,8 +326,6 @@ let Uses = [CC] in {
// Register stores.
let SimpleBDXStore = 1 in {
defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
- def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
- Requires<[FeatureHighWord]>;
def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
// These instructions are split after register allocation, so we don't