diff options
| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-13 16:57:53 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-13 16:57:53 +0000 |
| commit | 541c5de2fb57b2f459f0ec49f33a0ecce3532acd (patch) | |
| tree | 33f14bf5f3dc7b3198a668625c93ff35076acead /lib/Target/SystemZ | |
| parent | 1a362619f8f74267776a93f101ef32b69b53f5b3 (diff) | |
| download | llvm-541c5de2fb57b2f459f0ec49f33a0ecce3532acd.tar.gz llvm-541c5de2fb57b2f459f0ec49f33a0ecce3532acd.tar.bz2 llvm-541c5de2fb57b2f459f0ec49f33a0ecce3532acd.tar.xz | |
[SystemZ] Add the general form of BCR
At the moment this is just the MC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ')
| -rw-r--r-- | lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp | 13 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 3 |
2 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index fc7fbf98f5..fc3c38d2f3 100644 --- a/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -48,14 +48,11 @@ extern "C" void LLVMInitializeSystemZDisassembler() { } static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, - const unsigned *Regs, - bool isAddress = false) { + const unsigned *Regs) { assert(RegNo < 16 && "Invalid register"); - if (!isAddress || RegNo) { - RegNo = Regs[RegNo]; - if (RegNo == 0) - return MCDisassembler::Fail; - } + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateReg(RegNo)); return MCDisassembler::Success; } @@ -87,7 +84,7 @@ static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, true); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index a318aa1b73..eb416036bf 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -67,6 +67,8 @@ let isBranch = 1, isTerminator = 1, Uses = [CC] in { "brc\t$R1, $I2", []>; def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2), "brcl\t$R1, $I2", []>; + def AsmBCR : InstRR<0x07, (outs), (ins uimm8zx4:$R1, GR64:$R2), + "bcr\t$R1, $R2", []>; } // Fused compare-and-branch instructions. As for normal branches, @@ -117,6 +119,7 @@ multiclass CondExtendedMnemonic<bits<4> ccmask, string name> { "j"##name##"\t$I2", []>; def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg"##name##"\t$I2", []>; + def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>; } def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; |