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author | Evan Cheng <evan.cheng@apple.com> | 2007-05-16 21:53:07 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-05-16 21:53:07 +0000 |
commit | 02c602b333ed2a1a13a17981f3c3f2f5463d5e5c (patch) | |
tree | 9bf1b6ad5716a0c78dd1ac6b4776699e667de0ea /lib/Target/TargetInstrInfo.cpp | |
parent | 2eb80fa433fbc9257bb7ef236e48092981cc3b3c (diff) | |
download | llvm-02c602b333ed2a1a13a17981f3c3f2f5463d5e5c.tar.gz llvm-02c602b333ed2a1a13a17981f3c3f2f5463d5e5c.tar.bz2 llvm-02c602b333ed2a1a13a17981f3c3f2f5463d5e5c.tar.xz |
PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/TargetInstrInfo.cpp')
-rw-r--r-- | lib/Target/TargetInstrInfo.cpp | 33 |
1 files changed, 19 insertions, 14 deletions
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index fe5ee1d25e..d1413510ff 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -60,22 +60,27 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const { return MI; } -void TargetInstrInfo::PredicateInstruction(MachineInstr *MI, +bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI, std::vector<MachineOperand> &Cond) const { + bool MadeChange = false; const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); - assert((TID->Flags & M_PREDICABLE) && - "Predicating an unpredicable instruction!"); - - for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { - if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isReg()) - MO.setReg(Cond[j].getReg()); - else if (MO.isImm()) - MO.setImm(Cond[j].getImmedValue()); - else if (MO.isMBB()) - MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock()); - ++j; + if (TID->Flags & M_PREDICABLE) { + for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { + if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg()) { + MO.setReg(Cond[j].getReg()); + MadeChange = true; + } else if (MO.isImm()) { + MO.setImm(Cond[j].getImmedValue()); + MadeChange = true; + } else if (MO.isMBB()) { + MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock()); + MadeChange = true; + } + ++j; + } } } + return MadeChange; } |