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author | Evan Cheng <evan.cheng@apple.com> | 2011-06-28 19:10:37 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-28 19:10:37 +0000 |
commit | e837dead3c8dc3445ef6a0e2322179c57e264a13 (patch) | |
tree | 57adf441e9376d2922b205181d6bad180c5dc80a /lib/Target/TargetInstrInfo.cpp | |
parent | 9bbe4d6c004f25bc491e2583cce7bc91891f68c7 (diff) | |
download | llvm-e837dead3c8dc3445ef6a0e2322179c57e264a13.tar.gz llvm-e837dead3c8dc3445ef6a0e2322179c57e264a13.tar.bz2 llvm-e837dead3c8dc3445ef6a0e2322179c57e264a13.tar.xz |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/TargetInstrInfo.cpp')
-rw-r--r-- | lib/Target/TargetInstrInfo.cpp | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index 2cb89f4440..66f8f60723 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -24,22 +24,21 @@ using namespace llvm; // TargetInstrInfo //===----------------------------------------------------------------------===// -TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc, - unsigned numOpcodes) - : Descriptors(Desc), NumOpcodes(numOpcodes) { +TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes) { + InitMCInstrInfo(Desc, numOpcodes); } TargetInstrInfo::~TargetInstrInfo() { } const TargetRegisterClass* -TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum, +TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI) const { - if (OpNum >= TID.getNumOperands()) + if (OpNum >= MCID.getNumOperands()) return 0; - short RegClass = TID.OpInfo[OpNum].RegClass; - if (TID.OpInfo[OpNum].isLookupPtrRegClass()) + short RegClass = MCID.OpInfo[OpNum].RegClass; + if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) return TRI->getPointerRegClass(RegClass); // Instructions like INSERT_SUBREG do not have fixed register classes. @@ -135,13 +134,13 @@ void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } |