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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-11 16:34:08 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-11 16:34:08 +0000 |
commit | a6035773d8d29827a124e65c258adbf0dcbb1a5a (patch) | |
tree | 7e96180d5cc189add9ff33b5753122d491968fd2 /lib/Target/TargetRegisterInfo.cpp | |
parent | de0250728b1a9e69ca593168f1ea2ecef8e9bf95 (diff) | |
download | llvm-a6035773d8d29827a124e65c258adbf0dcbb1a5a.tar.gz llvm-a6035773d8d29827a124e65c258adbf0dcbb1a5a.tar.bz2 llvm-a6035773d8d29827a124e65c258adbf0dcbb1a5a.tar.xz |
Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/TargetRegisterInfo.cpp')
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 2395f2ba12..be8b582890 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -20,8 +20,10 @@ using namespace llvm; TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, - const char *const *subregindexnames) - : InfoDesc(ID), SubRegIndexNames(subregindexnames), + const char *const *SRINames, + const unsigned *SRILaneMasks) + : InfoDesc(ID), SubRegIndexNames(SRINames), + SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE) { } |