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| author | Manman Ren <mren@apple.com> | 2012-06-26 19:47:59 +0000 |
|---|---|---|
| committer | Manman Ren <mren@apple.com> | 2012-06-26 19:47:59 +0000 |
| commit | 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 (patch) | |
| tree | b575dce801938772f5cfd5bc9a8cbe5391474ccc /lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | |
| parent | ca578e7ba6b1e4ce955134e3fb1d5014942e5248 (diff) | |
| download | llvm-1f7a1b68a07ea6bdf521525a7928f4a8c5216713.tar.gz llvm-1f7a1b68a07ea6bdf521525a7928f4a8c5216713.tar.bz2 llvm-1f7a1b68a07ea6bdf521525a7928f4a8c5216713.tar.xz | |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 12f1961ed8..52506fa185 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -621,7 +621,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, VEX_X = 0x0; if (HasVEX_4VOp3) - VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); + // Instruction format for 4VOp3: + // src1(ModR/M), MemAddr, src3(VEX_4V) + // CurOp points to start of the MemoryOperand, + // it skips TIED_TO operands if exist, then increments past src1. + // CurOp + X86::AddrNumOperands will point to src3. + VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); break; case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM2m: case X86II::MRM3m: |