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| author | Reid Spencer <rspencer@reidspencer.com> | 2004-10-22 21:02:08 +0000 |
|---|---|---|
| committer | Reid Spencer <rspencer@reidspencer.com> | 2004-10-22 21:02:08 +0000 |
| commit | 8c2c3152d64aafe24b5b67cd7d670658eb65df18 (patch) | |
| tree | dc32473730cf8b02d1e11eabbfe86a4b963823e3 /lib/Target/X86/Makefile | |
| parent | 4d71b6611e9281c999f34712bfd014cc3c95ef3f (diff) | |
| download | llvm-8c2c3152d64aafe24b5b67cd7d670658eb65df18.tar.gz llvm-8c2c3152d64aafe24b5b67cd7d670658eb65df18.tar.bz2 llvm-8c2c3152d64aafe24b5b67cd7d670658eb65df18.tar.xz | |
Adjust to changes in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/Makefile')
| -rw-r--r-- | lib/Target/X86/Makefile | 48 |
1 files changed, 5 insertions, 43 deletions
diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile index dd745402fe..bdaf28c5e8 100644 --- a/lib/Target/X86/Makefile +++ b/lib/Target/X86/Makefile @@ -8,50 +8,12 @@ ##===----------------------------------------------------------------------===## LEVEL = ../../.. LIBRARYNAME = x86 -include $(LEVEL)/Makefile.common - TARGET = X86 - # Make sure that tblgen is run, first thing. -$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ - X86GenRegisterInfo.inc X86GenInstrNames.inc \ - X86GenInstrInfo.inc X86GenATTAsmWriter.inc \ - X86GenIntelAsmWriter.inc - -TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ - $(SourceDir)/../Target.td - -$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register names with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ - -$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register information header with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ +BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ + X86GenRegisterInfo.inc X86GenInstrNames.inc \ + X86GenInstrInfo.inc X86GenATTAsmWriter.inc \ + X86GenIntelAsmWriter.inc -$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register info implementation with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ - -$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction names with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ - -$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction information with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ - -$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td AT&T assembly writer with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@ - -$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td Intel assembly writer with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@ - -#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN) -# @echo "Building $(TARGET).td instruction selector with tblgen" -# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ +include $(LEVEL)/Makefile.common -clean:: - $(VERB) rm -f *.inc |