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author | Michael Liao <michael.liao@intel.com> | 2012-11-08 07:28:54 +0000 |
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committer | Michael Liao <michael.liao@intel.com> | 2012-11-08 07:28:54 +0000 |
commit | be02a90de17f857ba65bbd8a11653ca1bad30adc (patch) | |
tree | ca8ccf2e856410b18f269335eb1b8ed98c1c1426 /lib/Target/X86/X86ISelLowering.cpp | |
parent | 7629de3326318e533ab969abd1b0cbc569b3f3b7 (diff) | |
download | llvm-be02a90de17f857ba65bbd8a11653ca1bad30adc.tar.gz llvm-be02a90de17f857ba65bbd8a11653ca1bad30adc.tar.bz2 llvm-be02a90de17f857ba65bbd8a11653ca1bad30adc.tar.xz |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 920cbf28d0..52c9128c67 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12195,6 +12195,63 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, // private utility function +/// Utility function to emit xbegin specifying the start of an RTM region. +MachineBasicBlock * +X86TargetLowering::EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB) const { + DebugLoc DL = MI->getDebugLoc(); + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + + const BasicBlock *BB = MBB->getBasicBlock(); + MachineFunction::iterator I = MBB; + ++I; + + // For the v = xbegin(), we generate + // + // thisMBB: + // xbegin sinkMBB + // + // mainMBB: + // eax = -1 + // + // sinkMBB: + // v = eax + + MachineBasicBlock *thisMBB = MBB; + MachineFunction *MF = MBB->getParent(); + MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); + MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); + MF->insert(I, mainMBB); + MF->insert(I, sinkMBB); + + // Transfer the remainder of BB and its successor edges to sinkMBB. + sinkMBB->splice(sinkMBB->begin(), MBB, + llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); + sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); + + // thisMBB: + // xbegin sinkMBB + // # fallthrough to mainMBB + // # abortion to sinkMBB + BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB); + thisMBB->addSuccessor(mainMBB); + thisMBB->addSuccessor(sinkMBB); + + // mainMBB: + // EAX = -1 + BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1); + mainMBB->addSuccessor(sinkMBB); + + // sinkMBB: + // EAX is live into the sinkMBB + sinkMBB->addLiveIn(X86::EAX); + BuildMI(*sinkMBB, sinkMBB->begin(), DL, + TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) + .addReg(X86::EAX); + + MI->eraseFromParent(); + return sinkMBB; +} + // Get CMPXCHG opcode for the specified data type. static unsigned getCmpXChgOpcode(EVT VT) { switch (VT.getSimpleVT().SimpleTy) { @@ -13858,6 +13915,10 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case X86::MONITOR: return EmitMonitor(MI, BB); + // xbegin + case X86::XBEGIN: + return EmitXBegin(MI, BB); + // Atomic Lowering. case X86::ATOMAND8: case X86::ATOMAND16: |