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| author | Craig Topper <craig.topper@gmail.com> | 2012-01-09 00:11:29 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-01-09 00:11:29 +0000 |
| commit | 39f227e4dd98d36ed852175825c3a74c05614bd6 (patch) | |
| tree | 516770be90d8d7c5d8604dcbfb5b701d710c708e /lib/Target/X86/X86InstrFormats.td | |
| parent | a8224ddf80b3e62391ade8fe26c445d860710b86 (diff) | |
| download | llvm-39f227e4dd98d36ed852175825c3a74c05614bd6.tar.gz llvm-39f227e4dd98d36ed852175825c3a74c05614bd6.tar.bz2 llvm-39f227e4dd98d36ed852175825c3a74c05614bd6.tar.xz | |
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrFormats.td')
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index dc92cb53ce..76cae1870e 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -399,12 +399,12 @@ class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> // SS3AI - SSSE3 instructions with TA prefix. // // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version -// uses the MMX registers. We put those instructions here because they better -// fit into the SSSE3 instruction category rather than the MMX category. +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> - : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, + : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, Requires<[HasSSSE3]>; class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> @@ -569,6 +569,11 @@ class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm, // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. +// MMXPI - SSE 1 & 2 packed instructions for MMX with no AVX equivalents +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. No AVX equiv. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. No AVX equiv. +// MMXSS38I - SSSE3 instructions with T8 prefix for MMX registers. No AVX equiv. +// MMXSS3AI - SSSE3 instructions with TA prefix for MMX registers. No AVX equiv. class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>; @@ -590,3 +595,21 @@ class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; + +class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, + Domain d> + : I<o, F, outs, ins, asm, pattern, d> { + let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasXMMInt], [HasXMM]); +} +class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasXMMInt]>; +class MMXSSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasXMMInt]>; +class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3orAVX]>; +class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3orAVX]>; |